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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
PM4328
TECT3
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER
DATASHEET
PROPRIETARY AND CONFIDENTIAL ISSUE 1: AUGUST 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
CONTENTS 1 2 3 4 5 FEATURES...............................................................................................1 APPLICATIONS...................................................................................... 11 REFERENCES .......................................................................................12 APPLICATION EXAMPLES ....................................................................15 BLOCK DIAGRAM..................................................................................16 5.1 5.2 5.3 6 7 8 9 TOP LEVEL BLOCK DIAGRAM...................................................16 M13 MULTIPLEXER MODE BLOCK DIAGRAM..........................18 DS3 FRAMER ONLY BLOCK DIAGRAM.....................................18
DESCRIPTION .......................................................................................20 PIN DIAGRAM ........................................................................................25 PIN DESCRIPTION ................................................................................26 FUNCTIONAL DESCRIPTION ...............................................................55 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 T1 FRAMER (T1-FRMR)..............................................................55 E1 FRAMER (E1-FRMR) .............................................................55 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) .........62 BIT ORIENTED CODE DETECTOR (RBOC) ..............................63 HDLC RECEIVER (RDLC)...........................................................63 T1 ALARM INTEGRATOR (ALMI)................................................64 ELASTIC STORE (ELST) ............................................................65 SIGNALING ELASTIC STORES (RX-SIG-ELST AND TX_SIGELST)...........................................................................................65 SIGNALING EXTRACTOR (SIGX)...............................................66
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 9.27 9.28 9.29 9.30
RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ......67 BASIC TRANSMITTER (XBAS)...................................................67 E1 TRANSMITTER (E1-TRAN) ...................................................68 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) ....68 SIGNALING ALIGNER (SIGA) .....................................................68 BIT ORIENTED CODE GENERATOR (XBOC)............................69 HDLC TRANSMITTERS (TDPR) .................................................69 T1 AUTOMATIC PERFORMANCE REPORT GENERATION (APRM) ........................................................................................70 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR (RJAT, TJAT) ...........................................................................................71 TIMING OPTIONS (TOPS) ..........................................................77 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION (PRBS) ...................................................................77 PSEUDO RANDOM PATTERN GENERATION AND DETECTION (PRGD) ........................................................................................77 DS3 FRAMER (DS3-FRMR) ........................................................78 PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .....80 DS3 TRANSMITTER (DS3-TRAN) ..............................................81 M23 MULTIPLEXER (MX23)........................................................82 DS2 FRAMER (DS2-FRMR) ........................................................82 M12 MULTIPLEXER (MX12)........................................................84 EGRESS SYSTEM INTERFACE (ESIF) ......................................85 INGRESS SYSTEM INTERFACE (ISIF) ......................................91 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI) .....................................................................................................96
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9.31 9.32 9.33 9.34 9.35 10 11
INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI) .97 SCALEABLE BANDWIDTH INTERCONNECT PISO (SBIPISO).98 SCALEABLE BANDWIDTH INTERCONNECT SIPO (SBISIPO).98 JTAG TEST ACCESS PORT........................................................98 MICROPROCESSOR INTERFACE .............................................98
NORMAL MODE REGISTER DESCRIPTION ...................................... 118 TEST FEATURES DESCRIPTION ....................................................... 119 11.1 JTAG TEST PORT .....................................................................121
12
OPERATION.........................................................................................134 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 DS3 FRAME FORMAT...............................................................134 SERVICING INTERRUPTS .......................................................136 USING THE PERFORMANCE MONITORING FEATURES.......136 USING THE INTERNAL FDL TRANSMITTER ...........................140 USING THE INTERNAL DATA LINK RECEIVER.......................144 T1 AUTOMATIC PERFORMANCE REPORT FORMAT.............148 USING THE PER-CHANNEL SERIAL CONTROLLERS............150 T1/E1 FRAMER LOOPBACK MODES ......................................151 DS3 LOOPBACK MODES .........................................................154
12.10 SBI BUS DATA FORMATS.........................................................157 12.11 H-MVIP DATA FORMAT.............................................................166 12.12 SERIAL CLOCK AND DATA FORMAT .......................................170 12.13 PRGD PATTERN GENERATION ...............................................170 12.14 JTAG SUPPORT........................................................................175 13 FUNCTIONAL TIMING .........................................................................183
iii
PROPRIETARY AND CONFIDENTIAL
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 14 15 16 17 18 19
DS3 LINE SIDE INTERFACE TIMING .......................................183 DS3 SYSTEM SIDE INTERFACE TIMING ................................185 SBI DROP BUS INTERFACE TIMING .......................................187 SBI ADD BUS INTERFACE TIMING ..........................................188 EGRESS H-MVIP LINK TIMING ................................................188 INGRESS H-MVIP LINK TIMING ...............................................189 EGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ....190 INGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ...195
ABSOLUTE MAXIMUM RATINGS........................................................199 D.C. CHARACTERISTICS....................................................................200 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......202 TECT3 TIMING CHARACTERISTICS ..................................................206 ORDERING AND THERMAL INFORMATION ......................................234 MECHANICAL INFORMATION.............................................................235
LIST OF FIGURES FIGURE 1: CHANNELIZED DS3 CIRCUIT EMULATION APPLICATION .........15 FIGURE 2: HIGH DENSITY FRAME RELAY APPLICATION ............................15 FIGURE 3: TECT3 BLOCK DIAGRAM..............................................................17 FIGURE 4: M13 MULTIPLEXER BLOCK DIAGRAM ........................................18 FIGURE 5: DS3 FRAMER ONLY MODE BLOCK DIAGRAM ............................19 FIGURE 6: PIN DIAGRAM ................................................................................25 FIGURE 7: CRC MULTIFRAME ALIGNMENT ALGORITHM ............................59
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
FIGURE 8: DJAT JITTER TOLERANCE T1 MODES ........................................73 FIGURE 9: DJAT JITTER TOLERANCE E1 MODES........................................74 FIGURE 10: DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY T1 MODES..........................................................................................75 FIGURE 11: DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY E1 MODES..........................................................................................75 FIGURE 12: DJAT JITTER TRANSFER T1 MODES.........................................76 FIGURE 13: DJAT JITTER TRANSFER E1 MODES ........................................76 FIGURE 14: CLOCK MASTER: NXCHANNEL..................................................86 FIGURE 15: CLOCK MASTER: CLEAR CHANNEL..........................................87 FIGURE 16: CLOCK SLAVE: EFP ENABLED...................................................87 FIGURE 17: CLOCK SLAVE: EXTERNAL SIGNALING ....................................88 FIGURE 18: CLOCK SLAVE: CLEAR CHANNEL .............................................88 FIGURE 19: CLOCK SLAVE: H-MVIP...............................................................89 FIGURE 20: CLOCK MASTER: SERIAL DATA AND H-MVIP CCS ...................90 FIGURE 21: CLOCK MASTER: FULL T1/E1 ....................................................92 FIGURE 22: CLOCK MASTER: NXCHANNEL..................................................92 FIGURE 23: CLOCK MASTER: CLEAR CHANNEL..........................................93 FIGURE 24: CLOCK SLAVE: EXTERNAL SIGNALING ....................................93 FIGURE 25: CLOCK SLAVE: H-MVIP...............................................................94 FIGURE 26: CLOCK SLAVE: SERIAL DATA AND H-MVIP CCS ......................95 FIGURE 27: DS3 FRAME STRUCTURE ........................................................134 FIGURE 28: FER COUNT VS. BER (E1 MODE) ............................................138 FIGURE 29: CRCE COUNT VS. BER (E1 MODE)..........................................139
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
FIGURE 30: FER COUNT VS. BER (T1 ESF MODE).....................................139 FIGURE 31: CRCE COUNT VS. BER (T1 ESF MODE)..................................140 FIGURE 32: CRCE COUNT VS. BER (T1 SF MODE) ....................................140 FIGURE 33: TYPICAL DATA FRAME..............................................................147 FIGURE 34: EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE .........147 FIGURE 35: T1/E1 LINE LOOPBACK.............................................................152 FIGURE 36: T1/E1 DIAGNOSTIC DIGITAL LOOPBACK................................153 FIGURE 37: PER-CHANNEL LOOPBACK.....................................................154 FIGURE 38: DS3 DIAGNOSTIC LOOPBACK DIAGRAM ...............................155 FIGURE 39: DS3 LINE LOOPBACK DIAGRAM..............................................156 FIGURE 40: DS2 LOOPBACK DIAGRAM.......................................................156 FIGURE 41: PRGD PATTERN GENERATOR .................................................171 FIGURE 42: BOUNDARY SCAN ARCHITECTURE ........................................175 FIGURE 43: TAP CONTROLLER FINITE STATE MACHINE ..........................177 FIGURE 44: INPUT OBSERVATION CELL (IN_CELL) ...................................180 FIGURE 45: OUTPUT CELL (OUT_CELL) .....................................................181 FIGURE 46: BIDIRECTIONAL CELL (IO_CELL).............................................181 FIGURE 47: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 182 FIGURE 48: RECEIVE BIPOLAR DS3 STREAM............................................183 FIGURE 49: RECEIVE UNIPOLAR DS3 STREAM .........................................183 FIGURE 50: TRANSMIT BIPOLAR DS3 STREAM .........................................184 FIGURE 51: TRANSMIT UNIPOLAR DS3 STREAM.......................................184 FIGURE 52: FRAMER MODE DS3 TRANSMIT INPUT STREAM ..................185
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
FIGURE 53: FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH TGAPCLK ....................................................................................185 FIGURE 54: FRAMER MODE DS3 RECEIVE OUTPUT STREAM.................186 FIGURE 55: FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH RGAPCLK....................................................................................186 FIGURE 56: SBI DROP BUS T1 FUNCTIONAL TIMING ................................187 FIGURE 57: SBI DROP BUS DS3 FUNCTIONAL TIMING .............................187 FIGURE 58: SBI ADD BUS JUSTIFICATION REQUEST FUNCTIONAL TIMING .....................................................................................................188 FIGURE 59: EGRESS 8.192 MBPS H-MVIP LINK TIMING ............................189 FIGURE 60: INGRESS 8.192 MBPS H-MVIP LINK TIMING...........................189 FIGURE 61: T1 EGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE .....................................................................................................190 FIGURE 62: E1 EGRESS INTERFACE CLOCK MASTER : NXCHANNEL MODE190 FIGURE 63: T1 AND E1 EGRESS INTERFACE CLOCK MASTER: CLEAR CHANNEL MODE ........................................................................190 FIGURE 64: T1 EGRESS INTERFACE CLOCK SLAVE: EFP ENABLED MODE .....................................................................................................191 FIGURE 65: E1 EGRESS INTERFACE CLOCK SLAVE : EFP ENABLED MODE .....................................................................................................191 FIGURE 66: T1 EGRESS INTERFACE CLOCK SLAVE: EXTERNAL SIGNALING MODE ..........................................................................................192 FIGURE 67: E1 EGRESS INTERFACE CLOCK SLAVE : EXTERNAL SIGNALING MODE......................................................................192 FIGURE 68: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EFP ENABLED MODE ........................................................................193 FIGURE 69: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................194
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
FIGURE 70: T1 AND E1 EGRESS INTERFACE CLOCK SLAVE: CLEAR CHANNEL MODE ........................................................................194 FIGURE 71: T1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL MODE ..........................................................................................195 FIGURE 72: E1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL MODE ..........................................................................................195 FIGURE 73: T1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196 FIGURE 74: E1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196 FIGURE 75: T1 AND E1 INGRESS INTERFACE CLOCK MASTER: CLEAR CHANNEL MODE ........................................................................196 FIGURE 76: T1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................197 FIGURE 77: E1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................197 FIGURE 78: T1 INGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................198 FIGURE 79: MICROPROCESSOR INTERFACE READ TIMING....................203 FIGURE 80: MICROPROCESSOR INTERFACE WRITE TIMING ..................205 FIGURE 81: RSTB TIMING.............................................................................206 FIGURE 82: DS3 TRANSMIT INTERFACE TIMING .......................................208 FIGURE 83: DS3 RECEIVE INTERFACE TIMING.......................................... 211 FIGURE 84: SBI ADD BUS TIMING ................................................................214 FIGURE 85: SBI DROP BUS TIMING .............................................................216 FIGURE 86: SBI DROP BUS COLLISION AVOIDANCE TIMING ...................216 FIGURE 87: H-MVIP EGRESS DATA & FRAME PULSE TIMING...................218 FIGURE 88: H-MVIP INGRESS DATA TIMING ...............................................219 FIGURE 89: XCLK INPUT TIMING .................................................................220
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
FIGURE 90: EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE ..........................................................................................221 FIGURE 91: EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING MODE......................................................................222 FIGURE 92: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : NXCHANNEL MODE ...................................................................223 FIGURE 93: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR CHANNEL MODE ........................................................................224 FIGURE 94: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : SERIAL DATA AND H-MVIP CCS MODE ....................................225 FIGURE 95: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR CHANNEL MODE ........................................................................226 FIGURE 96: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES .......228 FIGURE 97: INGRESS INTERFACE TIMING - CLOCK MASTER MODES....229 FIGURE 98: TRANSMIT LINE INTERFACE TIMING ......................................230 FIGURE 99: JTAG PORT INTERFACE TIMING..............................................233 FIGURE 100: 324 PIN PBGA 23X23MM BODY..............................................235
LIST OF TABLES TABLE 1: E1-FRMR FRAMING STATES ..........................................................60 TABLE 2: REGISTER MEMORY MAP ..............................................................99 TABLE 3: INSTRUCTION REGISTER ............................................................121 TABLE 4: IDENTIFICATION REGISTER.........................................................122 TABLE 5: BOUNDARY SCAN CHAIN .............................................................122 TABLE 6: PMON COUNTER SATURATION LIMITS (E1 MODE) ...................137 TABLE 7: PMON COUNTER SATURATION LIMITS (T1 MODE) ...................137
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
TABLE 8: PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS .................................................................................148 TABLE 9: PERFORMANCE REPORT MESSAGE STRUCTURE NOTES......149 TABLE 10: PERFORMANCE REPORT MESSAGE CONTENTS ...................149 TABLE 11: STRUCTURE FOR CARRYING MULTIPLEXED LINKS ...............158 TABLE 12: T1 TRIBUTARY COLUMN NUMBERING ......................................158 TABLE 13: SBI T1 LINK RATE INFORMATION ..............................................160 TABLE 14: SBI T1 CLOCK RATE ENCODING ...............................................160 TABLE 15: DS3 LINK RATE INFORMATION ..................................................161 TABLE 16: DS3 CLOCK RATE ENCODING ...................................................161 TABLE 17: T1 FRAMING FORMAT.................................................................162 TABLE 18: T1 CHANNEL ASSOCIATED SIGNALING BITS ...........................164 TABLE 19: DS3 FRAMING FORMAT ..............................................................165 TABLE 20: DS3 BLOCK FORMAT ..................................................................166 TABLE 21: DS3 MULTI-FRAME STUFFING FORMAT ...................................166 TABLE 22: DATA AND CAS T1 H-MVIP FORMAT ..........................................166 TABLE 23: DATA AND CAS E1 H-MVIP FORMAT IN G.747 MODE ...............167 TABLE 24: CCS T1 H-MVIP FORMAT ............................................................168 TABLE 25: CCS E1 H-MVIP FORMAT IN G.747 MODE .................................168 TABLE 26: PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)........173 TABLE 27: REPETITIVE PATTERN GENERATION (PS BIT = 1)...................174 TABLE 28: ABSOLUTE MAXIMUM RATINGS ................................................199 TABLE 29: D.C. CHARACTERISTICS ............................................................200 TABLE 30: MICROPROCESSOR INTERFACE READ ACCESS ....................202
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
TABLE 31: MICROPROCESSOR INTERFACE WRITE ACCESS ..................204 TABLE 32: RTSB TIMING ...............................................................................206 TABLE 33: DS3 TRANSMIT INTERFACE TIMING..........................................206 TABLE 34: DS3 RECEIVE INTERFACE TIMING ............................................210 TABLE 35: SBI ADD BUS TIMING (FIGURE 84) ............................................213 TABLE 36: SBI DROP BUS TIMING (FIGURE 85 TO FIGURE 86) ................214 TABLE 37: H-MVIP EGRESS TIMING (FIGURE 87).......................................217 TABLE 38: H-MVIP INGRESS TIMING (FIGURE 88) .....................................218 TABLE 39: XCLK INPUT (FIGURE 89) ...........................................................220 TABLE 40: EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED MODE (FIGURE 90) ....................................................................221 TABLE 41: EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL SIGNALING (FIGURE 91) ...........................................................222 TABLE 42: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : NXCHANNEL MODE (FIGURE 92) .............................................223 TABLE 43: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR CHANNEL MODE (FIGURE 92) ..................................................224 TABLE 44: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : SERIAL DATA AND H-MVIP CCS MODE (FIGURE 92) ............................225 TABLE 45: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR CHANNEL MODE (FIGURE 92) ..................................................226 TABLE 46: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE 96)................................................................................................227 TABLE 47: INGRESS INTERFACE TIMING - CLOCK MASTER MODES (FIGURE 97)................................................................................229 TABLE 48: TRANSMIT LINE INTERFACE TIMING (FIGURE 98)...................230 TABLE 49: JTAG PORT INTERFACE .............................................................232
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
TABLE 50: ORDERING AND THERMAL INFORMATION ...............................234 TABLE 51: THERMAL INFORMATION - THETA JA VS. AIRFLOW ...............234
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
1
FEATURES * Integrates 28 T1 framers, 21 E1 framers and a full featured M13 multiplexer with DS3 framer in a single monolithic device for terminating DS3 multiplexed T1 or E1 streams. Four fundamental modes of operation: * * Up to 28 T1 streams M13 multiplexed into a serial DS3. Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data or H-MVIP system interfaces. DS3 M13 Multiplexer with ingress or egress per link monitoring. Unchannelized DS3 framer mode for access to the entire DS3 payload.
*
* * *
Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial interface system-side devices. Also supports a fractional T1 or E1 system interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping. Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and V5.1/V5.2 channels. Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams or 3 DS3 streams. Provides jitter attenuation in the T1 or E1 receive and transmit directions. Provides two independent de-jittered T1 or E1 recovered clocks for system timing and redundancy. Provides per-DS0 line loopback and per link diagnostic and line loopbacks. Provides an on-board programmable binary sequence generator and detector for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151.
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PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
*
Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152. Provides robbed bit signaling extraction and insertion on a per-DS0 basis. Provides programmable idle code substitution, data and sign inversion, and digital milliwatt code insertion on a per-DS0 basis. Supports the M23 and C-bit parity DS3 formats. Standalone unchannelized DS3 framer mode for access to the entire DS3 payload. When configured to operate as a DS3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits. DS3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed). Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver and the PM8313 D3MX M13 Multiplexer/Demultiplexer. Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant. 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40oC to 85oC) operation.
* * * * *
* *
* * * *
Each one of 28 T1 receiver sections: * * * Frames to DS-1 signals in SF and ESF formats. Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. Accepts gapped data streams to support higher rate demultiplexing.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
* * * * *
Provides Red, Yellow, and AIS alarm integration. Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link. Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis. Provides an HDLC interface with 128 bytes of buffering for terminating the facility data link. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. Provides an optional elastic store which may be used to time the ingress streams to a common clock and frame alignment, or to facilitate per-DS0 loopbacks. Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis. A pseudo-random sequence user selectable from 211 -1, 215 -1 or220 -1, may be detected in the T1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire T1 or any combination of DS0s within a framed T1. Line side interface is the DS3 interface via the M13 multiplex. System side interface is either serial clock and data, H-MVIP or SBI bus. Frames in the presence of and detects the "Japanese Yellow" alarm. Provides external access for up to two de-jittered recovered T1 clocks.
*
*
*
* * * *
Each one of 21 E1 receiver sections: * * Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications. Provides an HDLC interface with 128 bytes of buffering for terminating the national use bit data link.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
* * *
Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233. V5.2 link indication signal detection. Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line. Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction. Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16. Can be programmed to generate an interrupt on change of signaling state. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. A pseudo-random sequence user selectable from 211 -1, 215 -1 or220 -1, may be detected in the E1 stream in either the ingress or egress directions. The detector counts pattern errors using a 24-bit non-saturating PRBS error counter. The pseudo-random sequence can be the entire E1 or any combination of timeslots within the framed E1. Line side interface is the DS3 interface mutiplexed as per the G.747 recommendation. System side interface is either serial clock and data or H-MVIP. Provides external access for up to two de-jittered recovered E1 clocks.
* *
* *
*
* * *
Each one of 28 T1 transmitter sections: * May be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an N*8kHz reference. Provides minimum ones density through Bell (bit 7), GTE or "jammed bit 8" zero code suppression on a per-DS0 basis.
*
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
* * * * * * *
Provides a 128 byte buffer to allow insertion of the facility data link using the host interface. Supports transmission of the alarm indication signal (AIS) or the Yellow alarm signal in both SF and ESF formats. Provides a digital phase locked loop for generation of a low jitter transmit clock. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter. Automatically generates and transmits DS-1 performance report messages to ANSI T1.231and ANSI T1.408 specifications. Supports the alternate ESF CRC-6 calculation for Japanese applications.
11 15 20 A pseudo-random sequence user selectable from 2 -1, 2 -1 or 2 -1, may be inserted into the T1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire T1 or any combination of DS0s within the framed T1.
* *
Line side interface is through the DS3 Interface via the M13 multiplex. System side interface is either serial clock and data, H-MVIP or SBI bus.
Each one of 21 E1 transmitter sections: * * * * * Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path. Transmits G.704 basic and CRC-4 multiframe formatted E1. Supports unframed mode and framing bit, CRC, or data link by-pass. Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides a digital phase locked loop for generation of a low jitter transmit clock.
*
PROPRIETARY AND CONFIDENTIAL
5
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
*
A pseudo-random sequence user selectable from 211 -1, 215 -1 or 220 -1, may be inserted into the E1 stream in either the ingress or egress directions. The pseudo-random sequence can be inserted into the entire E1 or any combination of timeslots within the framed E1. Optionally inserts a datalink in the E1 national use bits. Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233 Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Line side interface is the DS3 interface mutiplexed as per the G.747 recommendation. System side interface is either serial clock and data or H-MVIP
* * * * *
DS3 Receiver Section: * Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2). Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable. Provides indication of M-frame boundaries from which M-subframe boundaries and overhead bit positions in the DS3 stream can be determined by external processing. Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate. Extracts valid X-bits and indicates far end receive failure (FERF). Accumulates up to 65,535 line code violation (LCV) events per second, 65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
* *
* * *
PROPRIETARY AND CONFIDENTIAL
6
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
* *
Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel. Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled or interrupt-driven operation. Selectable none, one or two address match detection on first byte of received packet. Programmable pseudo-random test-sequence detection-(up to 232 -1 bit length patterns conforming to ITU-T O.151 standards) and analysis features.
*
DS3 Transmit Section: * * Provides the overhead bit insertion for a DS3 stream. Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface Provides B3ZS encoding. Generates an B3Zs encoded 100... repeating pattern to aid in pulse mask testing. Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by internal register bits. Provides optional automatic insertion of far end receive failure (FERF) on detection of loss of signal (LOS), out of frame (OOF), alarm indication signal (AIS) or red alarm condition. Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error (FEBE) events. Supports insertion of bit-oriented codes in the C-bit parity far end alarm and control channel. Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation. Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards) or any
* * * *
*
* * *
PROPRIETARY AND CONFIDENTIAL
7
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
repeating pattern up to 32 bits. The test pattern can be framed or unframed. Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7. M23 Multiplexer Section: * * * * * * * Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream. Performs required bit stuffing/destuffing including generation and interpretation of C-bits. Includes required FIFO buffers for rate adaptation in the multiplex path. Allows insertion and detection of per DS2 payload loopback requests encoded in the C-bits to be activated under microprocessor control. Internally generates DS2 clock for use in integrated M13 or C-bit parity multiplex applications. Alternatively accepts external DS2 clock reference. Allows per DS2 alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control. Allows DS2 alarm indication signal (AIS) to be activated or cleared in the demultiplex direction automatically upon loss of DS3 frame alignment or signal. Supports C-bit parity DS3 format.
*
DS2 Framer Section: * Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2). Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a 10-3 bit error rate. Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF). Accumulates up to 255 DS2 M-bit or F-bit error events per second.
* * *
PROPRIETARY AND CONFIDENTIAL
8
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
DS2 Transmitter Section: * * * Generates the required X, F, and M bits into the transmitted DS2 bit stream. Allows inversion of inserted F or M bits for diagnostic purposes. Provides for transmission of far end receive failure (FERF) and alarm indication signal (AIS) under microprocessor control. Provides optional automatic insertion of far end receive failure (FERF) on detection of out of frame (OOF), alarm indication signal (AIS) or red alarm condition.
M12 Multiplexer Section: * * * * * * * Multiplexes four DS1 bit streams into a single M12 format DS2 bit stream. Performs required bit stuffing including generation and interpretation of Cbits. Includes required FIFO buffers for rate adaptation in the multiplex path. Performs required inversion of second and fourth multiplexed DS1 streams as required by ANSI T1.107 Section 7.2. Allows insertion and detection of per DS1 payload loopback requests encoded in the C-bits to be activated under microprocessor control. Allows per tributary alarm indication signal (AIS) to be activated or cleared for either direction under microprocessor control. Allows automatic tributary AIS to be activated upon DS2 out of frame.
Synchronous System Interfaces: * Provides seven 8Mb/s H-MVIP data interfaces for synchronous access to all the DS0s of all 28 T1 links or all timeslots of all 21 E1s. T1 DS0s are bundled from four T1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20, 21-24, 25-28). In normal mode, E1 timeslots are bundled from 4 E1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20 and 21 by itself). In G.747 mode, E1 timeslots are bundled from 3 E1 links in sequential order, spaced by a reserved timeslot on every 4th frame (i.e. 1-3/X, 4-6/X, 7-9/X, 10-12/X, 13-15/X, 16-18/X, 19-21/X).
PROPRIETARY AND CONFIDENTIAL
9
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
*
Provides seven 8Mb/s H-MVIP interfaces for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are repeated over the entire T1 or E1 multi-frame. Provides a single 8Mb/s H-MVIP interface for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface. All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals, CMV8MCLK, CMVFP, CMVFPC. H-MVIP access for Channel Associated Signaling is available with the Scaleable Bandwidth Interconnect bus as an optional replacement for CAS access over the SBI bus as well as with the H-MVIP data interface. Common Channel Signaling H-MVIP access is available with the SBI bus, serial PCM and H-MVIP data interfaces. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
*
*
*
*
Scaleable Bandwidth Interconnect (SBI) Bus: * Provides a high density byte serial interconnect for all framed and unframed TECT3 links. Utilizes an Add/Drop configuration to asynchronously mutliplex up to 84 T1s or 3 DS3s, equivalent to three TECT3s, with multiple payload or link layer processors. External devices can access unframed DS3, framed unchannelized DS3, unframed (clear channel) T1s or framed T1s over this interface. Framed and unframed T1 access can be selected on a per T1 basis. Synchronous access for T1 DS0 channels is supported in a locked format mode. Channel associated signaling bits for channelized T1 are explicitly identified across bus. Transmit timing is mastered either by the TECT3 or a layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1 or a DS3.
* * * * *
PROPRIETARY AND CONFIDENTIAL
10
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
2
APPLICATIONS * * * * * * High density T1 interfaces for multiplexers, multi-service switches, routers and digital modems. High density E1 interfaces for multiplexers, multi-service switches, routers and digital modems. Frame Relay switches and access devices (FRADS) M23 Based M13 Multiplexer C-Bit Parity Based M13 Multiplexer Channelized and Unchannelized DS3 Frame Relay Interfaces
PROPRIETARY AND CONFIDENTIAL
11
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
3 * * * * * *
REFERENCES American National Standard for Telecommunications - Digital Hierarchy Synchronous DS3 Format Specifications, ANSI T1.103-1993 American National Standard for Telecommunications - Digital Hierarchy Formats Specification, ANSI T1.107-1995 American National Standard for Telecommunications - Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1997 American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification, ANSI T1.403-1995 American National Standard for Telecommunications - Customer Installation-toNetwork - DS3 Metallic Interface Specification, ANSI T1.404-1994 American National Standard for Telecom-unications - Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer 1 Specification, ANSI T1.408-1990 Bell Communications Research, TR-TSY-000009 - Asynchronous Digital Multiplexes Requirements and Objectives, Issue 1, May 1986 Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue 1, October, 1987 Bell Communications Research - Alarm Indication Signal Requirements and Objectives, TR-TSY-000191 Issue 1, May 1986 Bell Communications Research - Wideband and Broadband Digital CrossConnect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993 Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, TR-NWT-000303, Issue 2, December, 1992 Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993 Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, TR-TSY-000820, Section 5.1, Issue 1, June 1990
* * * * *
* *
PROPRIETARY AND CONFIDENTIAL
12
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
* * * * * *
AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, TR 54016, September, 1989. AT&T - Accunet T1.5 - Service Description and Interface Specification, TR 62411, December, 1990 ITU Study Group XVIII - Report R 105, Geneva, 9-19 June 1992 ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates, May 1994 ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February, 1994. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991. ITU-T - Recommendation G.732 - Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993. ITU-T Recommendation G.747 - Second Order Digital Multiplex Equipment Operating at 6312kbit/s and Multiplexing Three Tributaries at 2048 kbit/s, 1988 ITU-T Recommendation G.775, - Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria, 11/94 ITU-T Recommendation G.823, - The Control of Jitter and Wander within Digital Networks which are Based on the 2048 kbit/s Hierarchy, 03/94 ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.
*
* * * * * * *
PROPRIETARY AND CONFIDENTIAL
13
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
*
ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Ex-hange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March -995. ITU-T - Recommend-tion I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993. ITU-T Recommendation O.151 - Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N x 64 kbit/s, October 1992 ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993 International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control procedures - Frame Structure PMC-Sierra Inc., PMC-1980577 - Saturn Compatible Scaleable Bandwidth Interface (SBI) Specification, Issue 3, 1998 TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 Specification, 1995. Nippon Telegraph and Telephone Corporation - Technical Reference for HighSpeed Digital Leased Circuit Services, Third Edition, 1990. GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994 GO-MVIP, H-MVIP Standard, Release1.1a, 1997
* * * * * * * * * * * * *
PROPRIETARY AND CONFIDENTIAL
14
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
4
APPLICATION EXAMPLES Figure 1: Channelized DS3 Circuit Emulation Application
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
PM73122 AAL1gator-32 ATM SAR
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
PM73122 AAL1gator-32 ATM SAR
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
SBI Bus
PM73122 AAL1gator-32 ATM SAR
Utopia Bus
Figure 2: High Density Frame Relay Application
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
PM7384 FREEDM 84P672 High Density HDLC Controller
DS3 LIU
PM4328 TECT3
28 T1/21 E1 Framer M13 Mux, DS3 framer
SBI Bus PCI Bus
High Density T1/E1 Frame Relay Port Card
PROPRIETARY AND CONFIDENTIAL
15
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
5 5.1
BLOCK DIAGRAM Top Level Block Diagram The diagram below shows the complete TECT3. T1 or E1 links can be multiplexed into a DS3 (E1s following the ITU-T G.747 recommendation). System side access to the T1s is available via the serial clock and data, H-MVIP or SBI bus interfaces. System side access to the E1s is available via the serial clock and data or H-MVIP interfaces. DS3 line side access is via the clock and data interface for line interface units. Unchannelized DS3 system side access is available through a serial clock and data interface or the SBI bus, both shown at the top of the diagram.
PROPRIETARY AND CONFIDENTIAL
16
DATASHEET
PMC-2011596
STANDARD PRODUCT
PROPRIETARY AND CONFIDENTIAL
XCLK CTCLK
TOPS Timing Options TJAT Digital Jitter Attenuator T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning TPSC Per-DS0 Controller ESIF Egress System Interface
A[13:0] D[7:0] RDB WRB CSB ALE INTB RSTB
MPIF MicroProcessor Interface
CECLK/CMV8MCLK CEFP/CMVFPB ED[1:28] ECLK[1:28]/ EFP[1:28]/ ESIG[1:28] MVED[1:7] CASED[1:7] CCSED
ISSUE 1
XBOC TDPR Bit Oriented HDLC Code Generator Transmitter
CLK52M
SBIPISO Parallel to Serial EXSBI SBI Egress Bus
Figure 3: TECT3 Block Diagram
T1-APRM
PMON Performance Monitor Counters RDLC HDLC Receiver Auto Performance Response Monitor
PRBS Pattern Generator/ Detector
SADATA[7:0] SADP SAPL SAV5 SAJUST_REQ
SBISIPO Serial to Parallel INSBI SBI Ingress Bus
RBOC Bit Oriented Code Detector ALMI Alarm Integrator TDPR Tx HDLC #1
17
MX23 M23 MUX/ DEMUX RJAT Digital Jitter Attenuator
ELST Elastic Store
XBOC Tx FEAC
SREFCLK SC1FP SDDATA[7:0] SDDP SDPL SDV5 SBIACT SBIDET[1:0]
TICLK TCLK TPOS/TDAT TNEG/TMFP
FRMR MX12 M12 DS2 Framer MUX/ DEMUX T1/E1-FRMR Frame Alignment, Alarm Extraction SIGX Signaling Extractor
B3ZS Encode
TRAN DS3 Transmit Framer
RCLK RPOS/RDAT RNEG/RLCV One of Seven FRMR/M12s One of 28 T1 or 21 E1 Framers
FRAM Framer RAM PMON Perf. Monitor
B3ZS Decode
FRMR DS3 Receive Framer
RPSC Per-DS0 Controller
ISIF Ingress System Interface
ID[1:28] IFP[1:28] ICLK[1:28]/ ISIG[1:28] MVID[1:7] CASID[1:7] CCSID CIFP CICLK/CMVFPC RECVCLK1 RECVCLK2
RBOC Rx FEAC
RDLC Rx HDLC
TDO TDI TCLK TMS TRSTB
JTAG Test Access Port
TFPO/TMFPO/ TGAPCLK TDATI TFPI/TMFPI RGAPCLK/RSCLK RDATO RFPO/RMFPO ROVRHD
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
PM4328 TECT3
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
5.2
M13 Multiplexer Mode Block Diagram Figure 4 shows the TECT3, configured as a M13 multiplexer, connected to a synchronous H-MVIP system side bus. In this example the TECT3 provides synchronous access to the fully channelized T1s (access to all DS0s) multiplexed into the DS3. There is also synchronous H-MVIP access to all channel associated signaling channels (CAS). An additional H-MVIP interface can be used to provide synchronous access to the common channel signaling channels (CCS), although this same information is available within the data HMVIP signals. Figure 4: M13 Multiplexer Block Diagram
XCLK CTCLK
CM V 8MC LK CM VFP B
TOP S Timing Options TJAT Digita l Jitter A tte nuator T1-XBAS/E1 -TRAN BasicTransm itte r: Frame Gene ration , Alarm Insertio n, Sign aling Ins ertio n, Tru nk Co n ditioning T PSC Per-D S0 Co ntroller E SIF Egress System Inte rface
MV ED[1:7] CA SED[1:7] CC SED
XBO C TDPR Bit O rie nte d HDLC C ode G enerator Transmitter
P MON Performance Mon itor Coun ters
RDLC HDLC Receiver
Auto Performance Response Monitor
T1-APRM
P RBS Pattern Gene rato r/ Detector
XBOC Tx FEAC
TDPR Tx HDLC TRAN DS3 Tra nsmit Framer M X23 M23 MUX/ DE MUX
RBOC Bit Oriented Code Detector
ALM I Ala rm Inte gra tor
TICLK TCLK TPOS/TDAT TNE G/TMFP
#1
MVID[1:7]
T1 /E1-FRM R Fram e Alignm en t, A larm Extraction ISIF Ingres s System Inte rface
B3 ZS Encode
B3 ZS
RC LK RPOS/RDAT RN EG/R LC V
De cod e
FRM R DS3 R ece ive Framer
FRMR MX12 M12 DS2 Framer MUX/ DEMUX
CAS ID[1:7] CCSID
RJAT Digita l Jitter A tte nua to r
One of Seven FRMR/M12s
RBOC Rx FEAC
RDLC Rx HDLC
P MON Perf. Monitor
One of 28 T1 or 21 E 1 Fr am er s
FRAM Framer RAM
ELST Elastic Store
S IG X Sign aling E xtracto r
R PSC Per-DS0 Controller
CIFP CICLK/C MVFPC REC VCLK 1 REC VCLK 2
5.3
DS3 Framer Only Block Diagram Figure 5 shows the TECT3 configured as a DS3 framer. In this mode the TECT3 provides access to the full DS3 unchannelized payload. The payload access (right side of diagram) has two clock and data interfacing modes, one utilizing a gapped clock to mask out the DS3 overhead bits and the second utilizing an ungapped clock with overhead indications on a separate overhead signal. The SBI bus can also be used to provide access to the unchannelized DS3.
PROPRIETARY AND CONFIDENTIAL
18
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 5: DS3 Framer Only Mode Block Diagram
TDP R Tx HD LC TIC LK TCLK TPO S/TD AT TNEG/TM FP TRAN DS3 Transm it Fram er FRM R DS3 R eceive Fram er PM ON Perf. M onitor
B3ZS E ncode
TD A TI TFP O/TMFPO /TG APC LK TFP I/T M FP I RG APCLK/RSCLK RD ATO RFPO /R MFPO RO VRHD
RCLK RPOS /RD AT RNEG /R LC V
B3ZS D ecode
RDLC Rx HDLC
PROPRIETARY AND CONFIDENTIAL
19
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
6
DESCRIPTION The PM4328 High Density T1/E1 Framer with Integrated M13 Multiplexer (TECT3) is a feature-rich device for use in any applications requiring high density link termination over T1 or E1 channelized DS3. The TECT3 supports asynchronous multiplexing and demultiplexing of 28 DS1s into a DS3 signal as specified by ANSI T1.107 and Bell Communications Research TR-TSY-000009. This device can also be configured as a DS3 framer, providing external access to the full DS3 payload. The TECT3 can be used as an M13 multiplexer with performance monitoring in either the ingress or egress direction for up to 28 T1s or 21 E1s. In this configuration the T1 and E1 transmit framers are disabled and either the ingress or egress T1 or E1 signals are routed to the T1 or E1 framers for performance monitoring purposes. Each of the T1 and E1 framers and transmitters is independently software configurable, allowing timing master and feature selection without changes to external wiring. This device is able to operate in T1 mode or E1 mode but not a mix of T1 and E1 modes. In the ingress direction, each of the 28 T1 framers is demultiplexed from a channelized DS3 . Each T1 framer can be configured to frame to either of the common DS1 signal formats: (SF, ESF) or to be bypassed (unframed mode). Each T1 framer detects and indicates the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. T1 performance monitoring with accumulation of CRC-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. The TECT3 also detects the presence of ESF bit oriented codes, and detects and terminates HDLC messages on the ESF data link. The HDLC messages are terminated in a 128 byte FIFO. An elastic store that optionally supports slip buffering and adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing and interrupt on signaling state change on a per-DS0 basis. The TECT3 also supports idle code substitution, digital milliwatt code insertion, data extraction, trunk conditioning, data sign and magnitude inversion, and pattern generation or detection on a perDS0 basis. In the egress direction, framing is generated for 28 T1s into the DS3. Each T1 transmitter frames to SF or ESF DS1 formats, or framing can be optionally
PROPRIETARY AND CONFIDENTIAL
20
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
disabled. The TECT3 supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion and zero-code suppression on a per-DS0 basis. PRBS generation or detection is supported on a framed and unframed T1 basis. In the ingress direction, each of the 21 E1 framers is extracted from the DS3 following the ITU-T G.747 recommendation. Each E1 framer detects and indicates the presence of remote alarm and AIS patterns and also integrates Red and AIS alarms. The E1 framers support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal. E1 performance monitoring with accumulation of CRC-4 errors, far end block errors and framing bit errors is provided. The TECT3 provides a receive HDLC controller for the detection and termination of messages on the national use bits. Detection of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300233 is supported. V5.2 link ID signal detection is also supported. An interrupt may be generated on any change of state of the Sa codewords. An elastic store for slip buffering and rate adaptation to backplane timing is provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided. In the egress direction, framing is generated for 21 E1s into the DS3 following the ITU-T G.747 recommendation.Each E1 transmitter generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS generation or detection is supported on a framed and unframed E1 basis. The TECT3 can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. Two low jitter recovered T1 clocks can be routed outside the TECT3 for network timing applications. Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s ingress/egress system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.
PROPRIETARY AND CONFIDENTIAL
21
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
In synchronous backplane systems 8Mb/s H-MVIP interfaces are provided for access to 672 DS0 channels, channel associated signaling (CAS) for all 672 DS0 channels and common channel signaling (CCS) for all 28 T1s. The DS0 data channel H-MVIP and CAS H-MVIP access is multiplexed with the serial PCM interface pins. The CCS signaling H-MVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1 slip buffers. A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus interconnects up to 84 T1s both synchronously or asynchronously. The SBI allows transmit timing to be mastered by either the TECT3 or link layer device connected to the SBI bus. This interconnect allows up to 3 TECT3s to be connected in parallel to provide the full complement of 84 T1s of traffic. In addition to framed T1s, the TECT3 can transport unframed T1 links and framed or unframed DS3 links over the SBI bus. When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TECT3 accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications. In the DS3 receive direction, the TECT3 frames to DS3 signals with a maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, C-bit parity errors, far end block errors, AIS, far end receive failure and idle code. The DS3 framer is an off-line framer, indicating both out of frame (OOF) and change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still indicated while the framer is OOF, based on the previous frame alignment. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC channels are detected and are available through the microprocessor port. Error event accumulation is also provided by the TECT3. Framing bit errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, and far end block errors are accumulated. Error accumulation continues even while the off-line framers are indicating OOF. The counters are intended to be polled once per second, and are sized so as not to saturate at a 10-3 bit error rate. Transfer of count values to holding registers is initiated through the microprocessor interface. In the DS3 transmit direction, the TECT3 inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Signals, Far End Receive Failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M sub-frame) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity application. Transmit timing is from an external reference or from the receive direction clock. The TECT3 also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo Random Binary Sequence (PRBS) can be inserted into a DS3 payload and checked in the receive DS3 payload for bit errors. A fixed 100100... pattern is available for insertion directly into the B3ZS encoder for proper pulse mask shape verification. When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of the DS3 signal. Bit stuffing and rate adaptation is performed. The C-bits are set appropriately, with the option of inserting DS2 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS3. AIS may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a stuffing ratio of 100%. Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far end receive failure is detected and M-bit and F-bit errors are accumulated. The DS2 framer is an off-line framer, indicating both OOF and COFA events. Error events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated while the DS2 framer is indicating OOF, based on the previous alignment. Each of the seven 6312 kbit/s multiplexers may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s into and out of a DS2 formatted signal. Tributary frequency deviations are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. When configured as a DS3 framer the unchannelized payload of the DS3 link is available to an external device.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
The TECT3 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
7
PIN DIAGRAM The TECT3 is currently planned to be packaged in a 324-pin PBGA package having a body size of 23mm by 23mm and a ball pitch of 1.0 mm. The center 36 balls are not used as signal I/Os and are thermal balls. Pin names and locations are defined in the Pin Description Table in section 8. Mechanical information for this package is in the section 19. Figure 6: Pin Diagram
22 21 20 19 18 17 16 15 14 13 12 11 10 A B C D E F G H J K L M N P R T U V W Y AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
9
8
7
6
5
4
3
2
1
324 PBGA
Bottom View
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
8
PIN DESCRIPTION Type Pin Function No.
Pin Name
DS3 Line Side Interface RCLK Input W5 Receive Input Clock (RCLK). RCLK provides the receive direction timing. RCLK is a DS3, nominally a 44.736 MHz, 50% duty cycle clock input. Positive Input Pulse (RPOS). RPOS represents the positive pulses received on the B3ZS-encoded DS3 when dual rail input format is selected. Receive Data Input (RDAT). RDAT represents the NRZ (unipolar) DS3 input data stream when single rail input format is selected. RPOS and RDAT are sampled on the rising edge of RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3 Master Receive Line Options register. RNEG/RLCV Input AB6 Negative Input Pulse (RNEG). RNEG represents the negative pulses received on the B3ZS-encoded DS3 when dual rail input format is selected. Line code violation (RLCV). RLCV represents receive line code violations when single rail input format is selected. RNEG and RLCV are sampled on the rising edge of RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3 Master Receive Line Options register. TCLK Output AA7 Transmit Clock (TCLK). TCLK provides timing for circuitry downstream of the DS3 transmitter of the TECT3. TCLK is nominally a 44.736 MHz, 50% duty cycle clock.
RPOS/RDAT
Input
Y7
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name TPOS/TDAT
Type
Pin Function No.
Output AB7 Transmit Positive Pulse (TPOS). TPOS represents the positive pulses transmitted on the B3ZS-encoded DS3 line when dual-rail output format is selected. Transmit Data Output (TDAT). TDAT represents the NRZ (unipolar) DS3 output data stream when single rail output format is selected. TPOS and TDAT are updated on the falling edge of TCLK by default but may be enabled to be updated on the rising edge of TCLK by setting the TRISE bit in the DS3 Master Transmit Line Options register. TPOS and TDAT are updated on TICLK rather than TCLK when the TICLK bit in the DS3 Master Transmit Line Options register is set.
TNEG/TMFP
Output W6
Transmit Negative Pulse (TNEG). TNEG represents the negative pulses transmitted on the B3ZS-encoded DS3 line when dual-rail output format is selected. Transmit Multiframe Pulse (TMFP). This signal marks the transmit M-frame alignment when configured for single rail operation. TMFP indicates the position of overhead bits in the transmit transmission system stream, TDAT. TMFP is high during the first bit (X1) of the multiframe. TNEG and TMFP are updated on the falling edge of TCLK by default but may be enabled to be updated on the rising edge of TCLK by setting the TRISE bit in the DS3 Master Transmit Line Options register. TNEG and TMFP are updated on TICLK rather than TCLK when the TICLK bit in the DS3 Master Transmit Line Options register is set.
TICLK
Input
AA6 Transmit input clock (TICLK). TICLK provides the transmit direction timing. TICLK is nominally a 44.736 MHz, 50% duty cycle clock. This clock is only required when using the DS3 transmitter with the DS3 line side interface. When not used this clock input should be connected to ground.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name XCLK/VCLK
Type Input
Pin Function No. E20 Crystal Clock Input (XCLK). This 24 times T1 or E1 clock provides timing for many of the T1 and E1 portions of TECT3. XCLK is nominally a 37.056 MHz 32ppm, 50% duty cycle clock when configured for T1 modes and is nominally a 49.152 MHz 32ppm, 50% duty cycle clock when configured for E1 modes. This clock is required for all operating modes of the TECT3. Test Vector Clock (VCLK). This signal is used during production testing.
DS3 System Side Interface RGAPCLK/RSCLK Output Y3 Framer Recovered Gapped Clock (RGAPCLK). RGAPCLK is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register and the RXGAPEN bit in the DS3 Master Unchannelized Interface Options register. RGAPCLK is the recovered clock and timing reference for RDATO. RGAPCLK is held either high or low during bit positions which correspond to overhead. Framer Recovered Clock (RSCLK). RSCLK is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register. RSCLK is the recovered clock and timing reference for RDATO, RFPO/RMFPO, and ROVRHD. This signal shares a signal pin with ICLK[1]. When enabled for unchannelized DS3 operation this signal will be RGAPCLK/RSCLK, otherwise it will be ICLK[1]. RDATO Output AA5 Framer Receive Data (RDATO). RDATO is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register. RDATO is the received data aligned to RFPO/RMFPO and ROVRHD. RDATO is updated on either the falling or rising edge of RGAPCLK or RSCLK, depending on the value of
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. the RSCLKR bit in the DS3 Master Unchannelized Interface Options register. By default RDATO will be updated on the falling edge of RGAPCLK or RSCLK. This signal shares a signal pin with ID[1] and MVID[1]. This signal will be RDATO only when enabled for unchannelized DS3 operation.
RFPO/RMFPO
Output AB5 Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO). RFPO/RMFPO is valid when the TECT3 is configured to be in framer only mode by setting the OPMODE[1:0] bits in the Global Configuration register. RFPO is aligned to RDATO and indicates the position of the first bit in each DS3 M-subframe. RMFPO is aligned to RDATO and indicates the position of the first bit in each DS3 M-frame. This is selected by setting the RXMFPO bit in the Master Framer Configuration Registers. RFPO/RMFPO is updated on either the falling or rising edge of RSCLK depending on the setting of the RSCLKR bit in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with IFP[1]. When enabled for unchannelized DS3 operation this signal will be RFPO/RMFPO, otherwise it will be IFP[1].
ROVRHD
Output Y6
Framer Receive Overhead (ROVRHD). ROVRHD is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register. ROVRHD will be high whenever the data on RDATO corresponds to an overhead bit position. ROVRHD is updated on the either the falling or rising edge of RSCLK depending on the setting of the RSCLKR bit in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ID[2] and CASID[1]. This signal will be ROVRHD only when enabled for unchannelized DS3 operation.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name TFPO/TMFPO/ TGAPCLK
Type
Pin Function No.
Output AB3 Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO). TFPO/TMFPO is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register and setting the TXGAPEN bit to 0 in the DS3 Master Unchannelized Interface Options register. TFPO pulses high for 1 out of every 85 clock cycles, giving a reference M-subframe indication. TMFPO pulses high for 1 out of every 4760 clock cycles, giving a reference M-frame indication. TFPO/TMFPO is updated on the falling edge of TICLK. TFPO/TMFPO can be configured to be updated on the rising edge of TICLK by setting the TDATIFALL bit to 1in the DS3 Master Unchannelized Interface Options register.. Framer Gapped Transmit Clock (TGAPCLK). TGAPCLK is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register and setting the TXGAPEN bit to 1 in the DS3 Master Unchannelized Interface Options register. TGAPCLK is derived from the transmit reference clock TICLK or from the receive clock if loop-timed. The overhead bit (gapped) positions are generated internal to the device. TGAPCLK is held high during the overhead bit positions. This clock is useful for interfacing to devices which source payload data only. TGAPCLK is used to sample TDATI and TFPI/TMFPI when TXGAPEN is set to 1. This signal shares a signal pin with ECLK[1]. When enabled for unchannelized DS3 operation this signal will be TFPO/TMFPO/TGAPCLK, otherwise it will be ECLK[1].
TDATI
Input
AB4 Framer Transmit Data (TDATI). TDATI contains the serial data to be transmitted when the TECT3 is configured as a DS3 framer by setting the
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. OPMODE[1:0] bits in the Global Configuration register. TDATI is sampled on the rising edge of TICLK if the TXGAPEN bit in the DS3 Master Unchannelized Interface Options register is logic 0. If TXGAPEN is logic 1, then TDATI is sampled on the rising edge of TGAPCLK. TDATI can be configured to be sampled on the falling edge of TICLK or TGAPCLK by setting the TDATIFALL bit in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ED[1] and MVED[1]. This signal will be TDATI only when enabled for unchannelized DS3 operation.
TFPI/TMFPI
Input
AA3 Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI). TFPI/TMFPI is valid when the TECT3 is configured as a DS3 framer by setting the OPMODE[1:0] bits in the Global Configuration register. TFPI indicates the position of all overhead bits in each DS3 M-subframe. TFPI is not required to pulse at every frame boundary. TMFPI indicates the position of the first bit in each DS3 M-frame. TMFPI is not required to pulse at every multiframe boundary. TFPI/TMFPI is sampled on the rising edge of TICLK if the TXGAPEN bit in the DS3 Master Unchannelized Interface Options register is logic 0. If TXGAPEN is logic 1, then TFPI/TMFPI is sampled on the rising edge of TGAPCLK. TFPI/TMFPI can be configured to be sampled on the falling edge of TICLK or TGAPCLK by setting the TDATIFALL bit to 1in the DS3 Master Unchannelized Interface Options register. This signal shares a signal pin with ED[2] and CASED[1]. This signal will be TFPI/TMFPI only when enabled for unchannelized DS3 operation.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No.
T1 and E1 System Side Serial Clock and Data Interface ICLK[1]/ISIG[1] Output Y3 Ingress Clocks (ICLK[1:28]). The Ingress Clocks are AB2 active when the external signaling interface is disabled. ICLK[2]/ISIG[2] ICLK[3]/ISIG[3] AB20 Each ingress clock is optionally a smoothed (jitter AB21 attenuated) version of the associated receive clock ICLK[4]/ISIG[4] ICLK[5]/ISIG[5] W22 from the DS3 multiplexer. When the Clock Master: Y20 NxChannel mode is active, ICLK[x] is a gapped version ICLK[6]/ISIG[6] ICLK[7]/ISIG[7] H22 of the smoothed receive clock. When Clock Master: F19 Full T1/E1 mode is active, IFP[x] and ID[x] are updated ICLK[8]/ISIG[8] W3 on the active edge of ICLK[x]. When the Clock Master: ICLK[9]/ISIG[9] AA1 NxDS0 mode is active, ID[x] is updated on the active ICLK[10]/ISIG[10] H3 edge of ICLK[x]. ICLK[11]/ISIG[11] H1 ICLK[12]/ISIG[12] L22 ICLK[13]/ISIG[13] K19 Ingress Signaling (ISIG[1:28]). When the Clock ICLK[14]/ISIG[14] F22 Slave: External Signaling mode is enabled, each ICLK[15]/ISIG[15] G20 ISIG[x] contains the extracted signaling bits for each ICLK[16]/ISIG[16] T3 channel in the frame, repeated for the entire ICLK[17]/ISIG[17] U1 superframe. Each channel's signaling bits are valid in ICLK[18]/ISIG[18] D1 bit locations 5,6,7,8 of the channel and are channelICLK[19]/ISIG[19] C1 aligned with the ID[x] data stream. ISIG[x] is updated ICLK[20]/ISIG[20] H19 on the active edge of the common ingress clock, ICLK[21]/ISIG[21] G19 CICLK. ICLK[22]/ISIG[22] E19 ICLK[23]/ISIG[23] F21 ICLK[24]/ISIG[24] K3 In E1 mode only ICLK[1:21] and ISIG[1:21] are used. ICLK[25]/ISIG[25] J4 ICLK[26]/ISIG[26] ICLK[1]/ISIG[1] shares a pin with the DS3 system E3 interface signal RGAPCLK/RSCLK. ICLK[27]/ISIG[27] D2 ICLK[28]/ISIG[28] IFP[1] IFP[2] IFP[3] IFP[4] IFP[5] IFP[6] IFP[7] IFP[8] IFP[9] IFP[10] IFP[11] Output AB5 Ingress Frame Pulse (IFP[1:28]). The IFP[x] outputs V3 are intended as timing references. W20 IFP[x] indicates the frame alignment or the superframe AA22 alignment of the ingress stream, ID[x]. Y21 W21 When Clock Master: Full T1/E1 mode is active, IFP[x] K22 is updated on the active edge of the associated K21 ICLK[x]. When Clock Master: NxDS0 mode is active, Y1 ICLK[x] is gapped during the pulse on IFP[x]. When W1 the Clock Slave ingress modes are active, IFP[x] is F4 updated on the active edge of CICLK. I the Clear
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name IFP[12] IFP[13] IFP[14] IFP[15] IFP[16] IFP[17] IFP[18] IFP[19] IFP[20] IFP[21] IFP[22] IFP[23] IFP[24] IFP[25] IFP[26] IFP[27] IFP[28] ID[1] ID[2] ID[3] ID[4] ID[5] ID[6] ID[7] ID[8] ID[9] ID[10] ID[11] ID[12] ID[13] ID[14] ID[15] ID[16] ID[17] ID[18] ID[19] ID[20] ID[21] ID[22] ID[23] ID[24]
Type
Pin Function No. G1 V20 Y22 K20 J19 W4 V1 E1 D9 U19 R22 J22 J20 K1 K2 D8 A9 Channel modes IFP[x] is not used. In E1 mode only IFP[1:21] is used. IFP[1] shares a pin with the DS3 system interface signal RFPO/RMFPO. IFP[20,27,28] shares pins with the SBI interface signals SDDP, SDPL, SDV5.
Output AA5 Ingress Data (ID[1:28]). Each ID[x] signal contains Y6 the recovered data stream which may have been AA20 passed through the elastic store. T19 When the Clock Slave ingress modes are active, the R19 ID[x] stream has passed through the elastic store and P20 is aligned to the common ingress timing. In this mode G22 ID[x] is updated on the active edge of CICLK. G21 Y2 When the Clock Master ingress modes are active, ID[x] W2 is aligned to the receive line timing and is updated on G4 the active edge of the associated ICLK[x]. H2 In E1 mode only ID[1:21] are used. P21 P22 ID[1,5,9,13,17,21,25] share pins with the H-MVIP data A12 signals MVID[1:7]. ID[2,6,10,14,18,22,26] share pins D12 with the H-MVIP CAS signals CASID[1:7]. ID[1] shares U2 a pin with the DS3 system interface signal RDATO. V4 ID[2] shares a pin with the DS3 system interface signal D11 ROVRHD. ID[15,16,19,20,23,24,27,28] shares pins A11 with the SBI interface bus SDDATA[7:0]. M19 L19 D10 A10
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name ID[25] ID[26] ID[27] ID[28] CICLK
Type
Pin Function No. J1 H4 B10 C10
Input
N1
Common Ingress Clock (CICLK). CICLK is either a 1.544MHz clock in T1 mode or a 2.048MHz clock in T1 or E1 modes, with optional gapping for adaptation to non-uniform backplane data streams. CICLK is common to all 28 T1 or 21 E1 framers. CIFP is sampled on the active edge of CICLK. When the Clock Slave ingress modes are active, ID[x], ISIG[x], and IFP[x] are updated on the active edge of CICLK. CICLK is a nominal 1.544 or 2.048 MHz clock +/50ppm with a 50% duty cycle. This signal shares a pin with the H-MVIP signal CMVFPC. By default this input is CICLK.
CIFP
Input
P4
Common Ingress Frame Pulse (CIFP). When the elastic store is enabled (Clock Slave mode is active on the ingress side), CIFP is used to frame align the ingress data to the system frame alignment. CIFP is common to all 28 T1 or 21 E1 framers. When frame alignment is required, a pulse at least 1 CICLK cycle wide must be provided on CIFP a maximum of once every frame (nominally 193 or 256 bit times). CIFP is sampled on the active edge of CICLK as selected by the CIFE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register.
CTCLK
Input
M3
Common Transmit Clock (CTCLK). This input signal is used as a reference transmit tributary clock which can be used in egress Clock Master modes. Depending on the configuration of the TECT3, CTCLK may be a line rate clock (so the transmit clock is generated directly from CTCLK, or from CTCLK after jitter attenuation), or a multiple of 8kHz (Nx8khz, where 1N256) so long as CTCLK is jitter-free when divided down to 8kHz (in which case the transmit clock is
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. derived by the DJAT PLL using CTCLK as a reference). The TECT3 may be configured to ignore the CTCLK input and utilize CECLK or one of the recovered Ingress clocks instead, RECVCLK1 and RECVCLK2. Receive tributary clock[x] is automatically substituted for CTCLK if line loopback is enabled.
CECLK
Input
N4
Common Egress Clock (CECLK). The common egress clock is used to time the egress interface when Clock Slave mode is enabled in the egress side. CECLK may be a 1.544MHz or 2.048MHz clock with optional gapping for adaptation from non-uniform system clocks. When the Clock Slave: EFP Enabled mode is active, CEFP and ED[x] are sampled on the active edge of CECLK, and EFP[x] is updated on the active edge of CECLK. When the Clock Slave: External Signaling mode is active, CEFP, ESIG[x] and ED[x] are sampled on the active edge of CECLK. CECLK is a nominal 1.544 or 2.048 MHz clock +/50ppm with a 50% duty cycle. This signal shares a pin with the H-MVIP signal CMV8MCLK. By default this input is CECLK.
CEFP
Input
M2
Common Egress Frame Pulse (CEFP). CEFP may be used to frame align the framers to the system backplane. If frame alignment only is required, a pulse at least 1 CECLK cycle wide must be provided on CEFP every 193 bit times for T1 mode or every 256 bit times for T1 and E1 modes (T1 mode using 2.048MHz clock). If superframe alignment is required, transmit superframe alignment must be enabled, and a pulse at least 1 CECLK cycle wide must be provided on CEFP every 12 or 24 frame times for T1 mode, on the first Fbit of the multiframe. CEFP is sampled on the active edge of CECLK as selected by the CEFE bit in the Master Common Egress Serial and H-MVIP Interface Configuration register. CEFP has no effect in the Clock Master egress modes.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. This signal shares a pin with the H-MVIP signal CMVFPB. By default this input is CEFP.
ED[1] ED[2] ED[3] ED[4] ED[5] ED[6] ED[7] ED[8] ED[9] ED[10] ED[11] ED[12] ED[13] ED[14] ED[15] ED[16] ED[17] ED[18] ED[19] ED[20] ED[21] ED[22] ED[23] ED[24] ED[25] ED[26] ED[27] ED[28]
Input
AB4 AA3 P19 N20 N21 N22 A7 A2 T2 R4 A3 B4 N19 M22 D6 C7 P2 M1 D4 B6 C20 E22 A5 B5 L1 L2 A4 C5
Egress Data (ED[1:28]). The egress data streams to be transmitted are input on these pins. When the Clock Master modes are active, ED[x] is sampled on the active edge of ECLK[x], except for Clock Master: Serial Data and H-MVIP CCS, when ED[x] is sampled on the active edge of ICLK[x]. When the Clock Slave egress modes are active, ED[x] is sampled on the active edge of CECLK, except for Clock Slave: Clear channel mode when ED[x] is sampled on the active edge of ECLK[x]. In E1 mode only ED[1:21] are used. ED[1,5,9,13,17,21,25] share pins with the H-MVIP data signals MVED[1:7]. ED[2,6,10,14,18,22,26] share pins with the H-MVIP CAS signals CASED[1:7]. ED[1] shares a pin with the DS3 system interface signal TDATI. ED[2] shares a pin with the DS3 system interface signal TFPI/TMFPI. ED[7,8,11,12,15,16,19,20,23,24,27,28] shares pins with the SBI interface add bus signals.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. AB3 Y4 Y19 AA21 AB22 V22 T21 T22 AB1 T1 G2 G3 U21 V19 D21 C21 U4 R1 D3 F1 T20 U22 B22 D20 L3 K4 E4 F2 Egress Clock (ECLK[1:28]). When the Clock Master mode is active, ECLK[x] is an output and is used to sample the associated egress data, ED[x]. ECLK[x] is a version of the transmit clock[x] which is generated from the receive clock or the common transmit clock, CTCLK. When in Clock Master: NxChannel mode, ECLK[x] is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels or 1 and 32 channel timeslots in the associated ED[x] stream. When Clock Master: Clear Channel is active ECLK[x] is not gapped. When in Clock Slave: Clear Channel mode this input is an input and is used to sampled ED[x]. ED[x] is sampled on the active edge of the associated ECLK[x]. Egress Frame Pulse (EFP[1:28]). When the Clock Slave: EFP Enabled mode is active, the EFP[1:28] outputs indicate the frame alignment or the superframe alignment of each of the 28 framers. EFP[x] is updated on the active edge of CECLK. Egress Signaling (ESIG[1:28]). When the Clock Slave: External Signaling mode is active, the ESIG[1:28] input carries the signaling bits for each channel in the transmit data frame, repeated for the entire superfram'. Each channel's signaling bits are in bit locations 5,6,7,8 of the channel and are frame-aligned by the common egress frame pulse, CEFP. ESIG[x] is sampled on the active edge of CECLK.
ECLK[1]/EFP[1]/ESIG[1] I/O ECLK[2]/EFP[2]/ESIG[2] ECLK[3]/EFP[3]/ESIG[3] ECLK[4]/EFP[4]/ESIG[4] ECLK[5]/EFP[5]/ESIG[5] ECLK[6]/EFP[6]/ESIG[6] ECLK[7]/EFP[7]/ESIG[7] ECLK[8]/EFP[8]/ESIG[8] ECLK[9]/EFP[9]/ESIG[9] ECLK[10]/EFP[10]/ESIG[10] ECLK[11]/EFP[11]/ESIG[11] ECLK[12]/EFP[12]/ESIG[12] ECLK[13]/EFP[13]/ESIG[13] ECLK[14]/EFP[14]/ESIG[14] ECLK[15]/EFP[15]/ESIG[15] ECLK[16]/EFP[16]/ESIG[16] ECLK[17]/EFP[17]/ESIG[17] ECLK[18]/EFP[18]/ESIG[18] ECLK[19]/EFP[19]/ESIG[19] ECLK[20]/EFP[20]/ESIG[20] ECLK[21]/EFP[21]/ESIG[21] ECLK[22]/EFP[22]/ESIG[22] ECLK[23]/EFP[23]/ESIG[23] ECLK[24]/EFP[24]/ESIG[24] ECLK[25]/EFP[25]/ESIG[25] ECLK[26]/EFP[26]/ESIG[26] ECLK[27]/EFP[27]/ESIG[27] ECLK[28]/EFP[28]/ESIG[28]
PROPRIETARY AND CONFIDENTIAL
37
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. ECLK[1]/EFP[1]/ESIG[1] shares a pin with the DS3 system interface output signal TFPO/TMFPO/TGAPCLK.
H-MVIP System Side Interfaces CMV8MCLK Input N4 Common 8M H-MVIP Clock (CMV8MCLK). The common 8.192 Mbps H-MVIP data provides the data clock for receive and transmit links configured for operation in 8.192 Mbps H-MVIP mode. CMV8MCLK is used to sample data on MVID[1:7], MVED[1:7], CASID[1:7], CASED[1:7], CCSID and CCSED. CMV8MCLK is nominally a 50% duty cycle clock with a frequency of 16.384MHz. The H-MVIP interfaces are enabled via the SYSOPT[2:0] bits in the Global Configuration register. This signal shares a pin with CECLK. By default this input is CECLK. CMVFPC Input N1 Common H-MVIP Frame Pulse Clock (CMVFPC). The common 8.192 Mbps H-MVIP frame pulse clock provides the frame pulse clock for receive and transmit links configured for operation in 8.192 Mbps H-MVIP mode. CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC must be aligned with the falling edge of CMV8MCLK with no more than 10ns skew. The H-MVIP interfaces are enabled via the SYSOPT[2:0] bits in the Global Configuration register. This signal shares a pin with CICLK. By default this input is CICLK. CMVFPB Input M2 Common H-MVIP Frame Pulse (CMVFPB). The active low common frame pulse for 8.192 Mbps HMVIP signals references the beginning of each frame for links operating in 8.192Mbps H-MVIP mode. The H-MVIP interfaces are enabled via the
PROPRIETARY AND CONFIDENTIAL
38
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. SYSOPT[2:0] bits in the Global Configuration register. The CMVFPB frame pulse occurs every 125us for a and is sampled on the falling edge of CMVFPC. This signal shares a pin with CEFP. By default this input is CEFP.
MVID[1] MVID[2] MVID[3] MVID[4] MVID[5] MVID[6] MVID[7]
Output AA5 R19 Y2 P21 U2 M19 J1
H-MVIP Ingress Data (MVID[1:7]). MVID[x] carries the recovered T1 or E1 channels which have passed through the elastic store. Each MVID[x] signal carries the channels of four complete T1s or E1s. MVID[x] carries the T1 or E1 data equivalent to ID[(4x-3):(4x)]. MVID[x] is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is updated on every second rising or falling edge of the common H-MVIP 16.384Mb /s clock, CMV8MCLK, as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. In E1 mode only MVID[1:6] are used. MVID[1:7] shares the same pins as ID[1,5,9,13,17,21,25].
CASID[1] CASID[2] CASID[3] CASID[4] CASID[5] CASID[6] CASID[7]
Output Y6 P20 W2 P22 V4 L19 H4
Channel Associated Signaling Ingress Data (CASID[1:7]). CASID[x] carries the channel associated signaling stream extracted from all the T1 or E1 channels. Each CASID[x] signal carries CAS for four complete T1s or E1s. CASID[x] carries the corresponding CAS values of the channel carried in MVID[x]. CASID[x] is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASID[x] is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface
PROPRIETARY AND CONFIDENTIAL
39
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. Configuration register. CASID[1:7] shares the same pins as ID[2,6,10,14,18,22,26].
CCSID
Output T4
Common Channel Signaling Ingress Data (CCSID). In T1 mode CCSID carries the 28 common channel signaling channels extracted from each of the 28 T1s. In E1 mode CCSID carries up to 3 timeslots (15,16, 31) from each of the 21 E1s. CCSID is formatted according to the H-MVIP standard. CCSID is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSID is updated on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register.
MVED[1] MVED[2] MVED[3] MVED[4] MVED[5] MVED[6] MVED[7]
Input
AB4 N21 T2 N19 P2 C20 L1
MVIP Egress Data (MVED[1:7]). The egress data streams to be transmitted are input on these pins. Each MVED[x] signal carries the channels of four complete T1s formatted according to the H-MVIP standard. MVED[x] carries the egress data equivalent to ED[(4x-3):(4x)]. MVID[x] is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. MVID[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. In E1 mode only MVED[1:6] are used. MVED[1:7] shares the same pins as ED[1,5,9,13,17,21,25].
CASED[1] CASED[2] CASED[3]
Input
AA3 Channel Associated Signaling Egress Data N22 (CASED[1:7]). CASED[x] carries the channel R4 associated signaling stream to be transmitted in the T1
PROPRIETARY AND CONFIDENTIAL
40
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name CASED[4] CASED[5] CASED[6] CASED[7]
Type
Pin Function No. M22 M1 E22 L2 DS0s or E1 timeslots. Each CASED[x] signal carries CAS for four complete T1s or E1s formatted according to the H-MVIP standard. CASED[x] carries the corresponding CAS values of the channel data carried in MVED[x]. CASED[x] is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CASED[x] is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register. CASED[1:7] shares the same pins as ED[2,6,10,14,18,22,26].
CCSED
Input
P1
Common Channel Signaling Egress Data (CCSED). In T1 mode CCSED carries the 28 common channel signaling channels to be transmitted in each of the 28 T1s. In E1 mode CCSED carries up to 3 timeslots (15,16, 31) to be transmitted in each of the 21 E1s. CCSED is formatted according to the H-MVIP standard. CCSED is aligned to the common H-MVIP 16.384Mb/s clock, CMV8MCLK, frame pulse clock, CMVFPC, and frame pulse, CMVFPB. CCSED is sampled on every second rising or falling edge of CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master Common Ingress Serial and H-MVIP Interface Configuration register.
PROPRIETARY AND CONFIDENTIAL
41
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No.
Recovered T1 and E1 Clocks RECVCLK1 Output D22 Recovered Clock 1 (RECVCLK1). This clock output is a recovered and de-jittered clock from any one of the 28 T1 framers or 21 E1 framers. Output C22 Recovered Clock 2 (RECVCLK2). This clock output is a recovered and de-jittered clock from any one of the 28 T1 framers or 21 E1 framers. Input B7 System Reference Clock (SREFCLK). This system reference clock is a nominal 19.44MHz +/-50ppm 50% duty cycle clock. This clock is common to both the add and drop sides of the SBI bus. System C1 Frame Pulse (SC1FP). The System C1 Frame Pulse is used to synchronize devices interfacing to the SBI bus. This signal is common to both the add and drop sides of the system SBI bus. By default, SC1FP is an input. The TECT3 can alternatively be configured to generate this frame pulse - as an output on SC1FP - for use by all other devices connected to the same SBI bus. Note that all devices interconnected via an SBI interface must be synchronized to an SC1FP signal from a single common source. As an input, SC1FP is sampled on the rising edge of SREFCLK. It normally indicates SBI mutiframe alignment, and thus should be asserted for a single SREFCLK cycle every 9720 SREFCLK cycles or some multiple thereof (i.e. every 9720*N SREFCLK cycles, where N is a positive integer). In synchronous SBI mode, however, SC1FP is used to indicate T1 signaling multiframe alignment, and thus should be asserted for a single SREFCLK cycle once every 12 SBI mutiframes (48 T1 frames or 116640 SREFCLK cycles). As an output, SC1FP is generated on the rising edge
RECVCLK2
Scaleable Bandwidth Interconnect Interface SREFCLK
SC1FP
I/O
A6
PROPRIETARY AND CONFIDENTIAL
42
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. of SREFCLK. It normally indicates SBI mutiframe alignment by pulsing high once every 9720 SREFCLK cycles. In synchronous SBI mode, however, SC1FP is used to indicate T1 signaling multiframe alignment by pulsing once every 12 SBI mutiframes (48 T1 frames or 116640 SREFCLK cycles).
SADATA[0] SADATA[1] SADATA[2] SADATA[3] SADATA[4] SADATA[5] SADATA[6] SADATA[7]
Input
D6 C7 D4 B6 A5 B5 A4 C5
System Add Bus Data (SADATA[7:0]). The System add data bus is a time division multiplexed bus which carries the T1 and DS3 tributary data is byte serial format over the SBI bus structure. This device only monitors the add data bus during the timeslots assigned to this device. SADATA[7:0] is sampled on the rising edge of SREFCLK. This bus shares pins with ED[15,16,19,20,23,24,27,28].
SADP
Input
A2
System Add Bus Data Parity (SADP). The system add bus signal carries the even or odd parity for the add bus signals SADATA[7:0], SAPL and SAV5. The TECT3 monitors parity across all links on the add bus. SADP is sampled on the rising edge of SREFCLK. This signal shares a pin with signal ED[8].
SAPL
Input
B4
System Add Bus Payload Active (SAPL). The add bus payload active signal indicates valid data within the SBI bus structure. This signal must be high during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to indicate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to indicate positive timing adjustments between the tributary rate and the fixed SBI bus structure. The TECT3 only monitors the add bus payload active signal during the tributary timeslots assigned to this device. SAPL is sampled on the rising edge of SREFCLK.
PROPRIETARY AND CONFIDENTIAL
43
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. This signal shares a pin with signal ED[12]. A3
SAV5
Input
System Add Bus Payload Indicator (SAV5). The add bus payload indicator locates the position of the floating payloads for each tributary within the SBI bus structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure. All timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the SAPL signal. The TECT3 only monitors the add bus payload Indicator signal during the tributary timeslots assigned to this device. SAV5 is sampled on the rising edge of SREFCLK. This signal shares a pin with signal ED[11].
SAJUST_REQ
Output D7 Tristate
System Add Bus Justification Request (SAJUST_REQ). The justification request signals the Link Layer device to speed up, slow down or maintain the rate which it is sending data to the TECT3. This is only used when the TECT3 is the timing master for the tributary transmit direction. This active high signal indicates negative timing adjustments when asserted high during the V3 or H3 octet of the tributary. In response to this the Link Layer device sends an extra byte in the V3 or H3 octet of the next SBI bus multi-frame. Positive timing adjustments are requested by asserting justification request high during the octet following the V3 or H3 octet. The Link Layer device responds to this request by not sending an octet during the V3 or H3 octet of the next multi-frame. The TECT3 only drives the justification request signal during the tributary timeslots assigned to this device. SAJUST_REQ is updated on the rising edge of SREFCLK.
PROPRIETARY AND CONFIDENTIAL
44
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name SDDATA[0] SDDATA[1] SDDATA[2] SDDATA[3] SDDATA[4] SDDATA[5] SDDATA[6] SDDATA[7]
Type
Pin Function No.
Output A12 System Drop Bus Data (SDDATA[7:0]). The System Tristate D12 drop data bus is a time division multiplexed bus which D11 carries the T1 and DS3 tributary data is byte serial A11 format over the SBI bus structure. This device only D10 drives the data bus during the timeslots assigned to A10 this device. B10 SDDATA[7:0] is updated on the rising edge of C10 SREFCLK. This bus shares pins with ID[15,16,19,20,23,24,27,28]. Output D9 Tristate System Drop Bus Data Parity (SDDP). The system drop bus signal carries the even or odd parity for the drop bus signals SDDATA[7:0], SDPL and SDV5. The TECT3 only drives the data bus parity during the timeslots assigned to this device unless configured for bus master mode. In this case, all undriven links should be driven externally with correctly generated parity. SDDP is updated on the rising edge of SREFCLK. This signal shares a pin with IFP[20].
SDDP
SDPL
Output D8 Tristate
System Drop Bus Payload Active (SDPB). The payload active signal indicates valid data within the SBI bus structure. This signal is asserted during all octets making up a tributary. This signal goes high during the V3 or H3 octet of a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI bus structure. This signal goes low during the octet after the V3 or H3 octet of a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI bus structure. The TECT3 only drives the payload active signal during the tributary timeslots assigned to this device. SDPL is updated on the rising edge of SREFCLK. This signal shares a pin with IFP[27].
SDV5
Output A9 Tristate
System Drop Bus Payload Indicator (SDV5). The payload indicator locates the position of the floating payloads for each tributary within the SBI bus
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. structure. Timing differences between the tributary timing and the synchronous SBI bus are indicated by adjustments of this payload indicator relative to the fixed SBI bus structure. All timing adjustments indicated by this signal are accompanied by appropriate adjustments in the SDPL signal. The TECT3 only drives the payload Indicator signal during the tributary timeslots assigned to this device. SDV5 is updated on the rising edge of SREFCLK. This signal shares a pin with IFP[28].
SBIACT
Output A8
SBI Output Active (SBIACT). The SBI Output Active indicator is high whenever the TECT3 is driving the SBI drop bus signals. This signal is used by other TECT3s or other SBI devices to detect SBI configuration problems by detecting other devices driving the SBI bus during the same tributary as the device listening to this signal. This output is updated on the rising edge or SREFCLK. 52MHz Clock Reference (CLK52M). The 52Mhz clock reference is used to generate a gapped DS3 clock when receiving a DS3 from the SBI bus interface. This clock has two nominal values. The first is a nominal 51.84MHz 50% duty cycle clock. The second is a nominal 44.928MHz 50% duty cycle clock. When this clock is not used this input must be connected to ground.
CLK52M
Input
P3
SBIDET[0] SBIDET[1]
Input
C8 A7
SBI Bus Activity Detection (SBIDET[1:0]). The SBI bus activity detect input detects tributary collisions between devices sharing the same SBI bus. Each SBI device driving the bus also drives an SBI active signal (SBIACT). This pair of activity detection inputs monitors the active signals from two other SBI devices. When unused this signal should be connected to ground.
PROPRIETARY AND CONFIDENTIAL
46
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No. A collision is detected when either of SBIDET[1:0] signals are active concurrently with this device driving SBIACT. When collisions occur the SBI drivers are disabled and an interrupt is generated to signal the collision. These signals are sampled on the rising edge of SREFCLK. SBIDET[1] is shared with serial interface signal ED[7].
Microprocessor Interface INTB Output A16 Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is OD detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source. Input D16 Active Low Chip Select (CSB). This signal is low during TECT3 register accesses. CSB has an integral pull up resistor. B16 Active Low Read Enable (RDB). This signal is low during TECT3 register read accesses. The TECT3 drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. C15 Active Low Write Strobe (WRB). This signal is low during a TECT3 register write access. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low.
CSB
RDB
Input
WRB
Input
PROPRIETARY AND CONFIDENTIAL
47
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] RSTB
Type I/O
Pin Function No. C14 Bidirectional Data Bus (D[7:0]). This bus provides B14 TECT3 register read and write accesses. A14 D14 C13 B13 A13 D13 A17 C16 D18 D19 B17 A18 A19 A20 C18 B19 B20 A21 C19 B21 Address Bus (A[13:0]). This bus selects specific registers during TECT3 register accesses. Signal A[13] selects between normal mode and test mode register access. A[13] has an integral pull down resistor.
Input
Input
A22 Active Low Reset (RSTB). This signal provides an asynchronous TECT3 reset. RSTB is a Schmitt triggered input with an integral pull up resistor. D17 Address Latch Enable (ALE). This signal is active high and latches the address bus A[13:0] when low. When ALE is high, the internal address latches are transparent. It allows the TECT3 to interface to a multiplexed address/data bus. The ALE input has an integral pull up resistor. C3 Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port.
ALE
Input
JTAG Interface TCK Input
PROPRIETARY AND CONFIDENTIAL
48
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name TMS
Type Input
Pin Function No. C2 Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. Test Data Input (TDI). This signal carries test data into the TECT3 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. Test Data Output (TDO). This signal carries test data out of the TECT3 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress. Active low Test Reset (TRSTB). This signal provides an asynchronous TECT3 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB must be connected to the RSTB input.
TDI
Input
C4
TDO
Output B3
TRSTB
Input
B1
Miscellaneous Pins NO CONNECT A1 No Connect. These pins are not connected to any B2 internal logic. A11 AB11 AB8 W7 W8 AB9 W9 Y10 AA10 AB10 W10 Y11
PROPRIETARY AND CONFIDENTIAL
49
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name
Type
Pin Function No.
Power and Ground Pins VDD3.3[17] VDD3.3[16] VDD3.3[15] VDD3.3[14] VDD3.3[13] VDD3.3[12] VDD3.3[11] VDD3.3[10] VDD3.3[9] VDD3.3[8] VDD3.3[7] VDD3.3[6] VDD3.3[5] VDD3.3[4] VDD3.3[3] VDD3.3[2] VDD3.3[1] VDD2.5[8] VDD2.5[7] VDD2.5[6] VDD2.5[5] VDD2.5[4] VDD2.5[3] VDD2.5[2] VDD2.5[1] VSS3.3[45] VSS3.3[44] VSS3.3[43] VSS3.3[42] VSS3.3[41] VSS3.3[40] VSS3.3[39] VSS3.3[38] VSS3.3[37] VSS3.3[36] VSS3.3[35] VSS3.3[34] VSS3.3[33] VSS3.3[32] Power N2 Power (VDD3.3[17:1]). The VDD3.3[17:1] pins should AA12 be connected to a well decoupled +3.3V DC power L21 supply. C12 F3 M4 U3 Y5 AA9 AA14 Y18 U20 M21 F20 C17 B11 D5 Power J2 Power (VDD2.5[8:1]). The VDD2.5[8:1] pins should R2 be connected to a well-decoupled +2.5V DC power AA8 supply. AA15 R21 H21 A15 C9 Ground N3 Ground (VSS3.3[45:1]). The VSS3.3[45:1] pins Y12 should be connected to GND. L20 B12 E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21
PROPRIETARY AND CONFIDENTIAL
50
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name VSS3.3[31] VSS3.3[30] VSS3.3[29] VSS3.3[28] VSS3.3[27] VSS3.3[26] VSS3.3[25] VSS3.3[24] VSS3.3[23] VSS3.3[22] VSS3.3[21] VSS3.3[20] VSS3.3[19] VSS3.3[18] VSS3.3[17] VSS3.3[16] VSS3.3[15] VSS3.3[14] VSS3.3[13] VSS3.3[12] VSS3.3[11] VSS3.3[10] VSS3.3[9] VSS3.3[8] VSS3.3[7] VSS3.3[6] VSS3.3[5] VSS3.3[4] VSS3.3[3] VSS3.3[2] VSS3.3[1] VSSQ[4] VSSQ[3] VSSQ[2] VSSQ[1]
Type
Pin Function No. M20 J21 E21 B18 D15 C11 B8 C6 W12 W13 AA13 Y13 W14 AB14 W15 W16 AB15 W17 AB16 Y16 AA16 AB17 AB13 AB12 AA17 AB18 W18 AA18 AB19 W19 AA2
Ground N3 Ground (VSSQ[4:1]). The VSSQ[4:1] pins should be Y12 connected to GND. L20 B12
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name VSS2.5[8] VSS2.5[7] VSS2.5[6] VSS2.5[5] VSS2.5[4] VSS2.5[3] VSS2.5[2] VSS2.5[1] VSS[36] VSS[35] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30] VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4]
Type
Pin Function No. J3 Ground (VSS2.5[8:1]). The VSS2.5[8:1] pins should R3 be connected to GND. Y8 Y15 R20 H20 B15 B9 J14 Thermal Ground (VSS). The VSS[36:1] pins should J13 be connected to a ground plane for enhanced thermal J12 conductivity. J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin Name VSS[3] VSS[2] VSS[1]
Type
Pin Function No. P11 P10 P9
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
NOTES ON PIN DESCRIPTIONS: 1. All TECT3 inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels. 2. All TECT3 outputs and bi-directionals have at least 2 mA drive capability. The bidirectional data bus outputs, D[7:0], have 4 mA drive capability. The outputs TCLK, TPOS/TDAT, TNEG/TMFP, RGAPCLK/RSCLK, RDATAO, RFPO/RMFPO, ROVRHD, TFPO/TMFPO/TGAPCLK, SBIACT, RECVCLK1, RECVCLK2, MVID[7:0], CASID[7:0], CCSID and INTB have 4 mA drive capability. The SBI outputs , SDDATA[7:0], SDDP, SDPL, SDV5, and SAJUST_REQ, have 8 mA drive capability. The bidirectional SBI signal SC1FP has 8 mA drive capability. 3. IOL = -2mA for others. 4. Inputs RSTB, ALE, TMS, TDI, TRSTB and CSB have internal pull-up resistors. 5. Input A[13] has an internal pull-down resistor. 6. All unused inputs should be connected to GROUND. 7. All TECT3 outputs can be tristated under control of the IEEE P1149.1 test access port, even those which do not tristate under normal operation. All outputs and bi-directionals are 5 V tolerant when tristated. 8. Power to the VDD3.3 and VDDQ pins should be applied before power to the VDD2.5 pins is applied. Similarly, power to the VDD2.5 pins should be removed before power to the VDD3.3 and VDDQ pins are removed. 9. All TECT3 inputs are 5V tolerant.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9 9.1
FUNCTIONAL DESCRIPTION T1 Framer (T1-FRMR) The T1 framing function is provided by the T1-FRMR block. This block searches for the framing bit position in the ingress stream. It works in conjunction with the FRAM block to search for the framing bit pattern in the standard superframe (SF), or extended superframe (ESF) framing formats. When searching for frame, the FRMR simultaneously examines each of the 193 (SF) or each of the 772 (ESF) framing bit candidates. The FRAM block is addressed and controlled by the FRMR while frame synchronization is acquired. The time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. For SF format, the T1-FRMR block will determine frame alignment within 4.4ms 99 times out of 100. For ESF format, the T1-FRMR will determine frame alignment within 15 ms 99 times out of 100. Once the T1-FRMR has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or a CRC-6 error in ESF), and severely errored framing events. The T1-FRMR also detects out-offrame, based on a selectable ratio of framing bit errors. The T1-FRMR can also be disabled to allow reception of unframed data.
9.2
E1 Framer (E1-FRMR) The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream. Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
on user-selectable criteria. The reframe operation can be initiated by software (via the E1-FRMR Frame Alignment Options Register), by excessive CRC errors, or when CRC multiframe alignment is not found within 400 ms. The E1-FRMR also identifies the position of the frame, the CAS multiframe, and the CRC multiframe. The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe), and stores them in the E1-FRMR International/National Bits register and the E1-FRMR Extra Bits register. Moreover, the FRMR also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe. The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms. An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF, OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, TS16AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe. Basic Frame Alignment Procedure The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
The algorithm finds frame alignment by using the following sequence: 1. Search for the presence of the correct 7-bit FAS (`0011011'); 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (NFAS) TS 0 byte is a logic 1; 3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame. If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS. Once frame alignment is found, the block sets the OOF indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of frame alignment if 3 consecutive FASs have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. The E1-FRMR can be forced to initiate a basic frame search at any time when any of the following conditions are met: * * * the software re-frame bit in the E1-FRMR Frame Alignment Options register goes to logic 1; the CRC Frame Find Block is unable to find CRC multiframe alignment; or the CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame under that condition.
CRC Multiframe Alignment Procedure The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1-FRMR declares loss of CRC multiframe alignment if basic frame alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern. Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 7.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 7: CRC Multiframe Alignment Algorithm
Out of Frame
3 consecutive FASor NFAS errors; manual reframe; or excessive CRC errors
FAS_Find_1
FA S found NF AS not found nex t fram e
FAS_F ind_1_Pa r
FA S found NF AS not found nex t fram e
NFAS_Find
NF AS found nex t fram e FA S not found nex t fram e
NFAS_Find_Par
NF AS found nex t fram e FA S not found nex t fram e
FAS_Find_2
FA S found nex t fram e 8ms ex pire
Start 400ms timer and 8ms timer
FAS_Find_2_Par
FA S found nex t fram e
Start 8ms timer
BFA
CR CMF A
8m s expire and NOT( 400 ms exp ire)
Reset BFA to most recently found alignment
BFA_Par
400m s expire
CR CM FA_ Par
CRCto CRC Interworking
CR CM FA_ Par (Op tional setting)
CRCto non-C RC Interworking
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 1: E1-FRMR Framing States State FAS_Find_1 NFAS_Find FAS_Find_2 BFA CRC to CRC Interworking FAS_Find_1_Par NFAS_Find_Par FAS_Find_2_Par BFA_Par CRC to non-CRC Interworking Out of Frame Yes Yes Yes No No No No No No No Out of Offline Frame No No No No No Yes Yes Yes No No
The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at each stage of the CRC multiframe alignment algorithm are shown in Table 1. From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared. If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment). Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
optionally set to either halt searching for CRC multiframe altogether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct. AIS Detection When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0. Signaling Frame Alignment Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct CAS alignment pattern, namely four zeros ("0000") in the first four bit positions of timeslot 16. Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost. National Bit Extraction The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
corresponding register values are updated upon generation of the CRC submultiframe interrupt. This E1-FRMR also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are zeros. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones. Alarm Integration The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms ( 6 ms). The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate. The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs. The E1-FRMR can also be disabled to allow reception of unframed data. 9.3 Performance Monitor Counters (T1/E1-PMON) The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the PMON transfers the counter values into
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, an OVERRUN register bit is asserted. Generation of the transfer clock within the TECT3 chip is performed by writing to any counter register location or by writing to the Global PMON Update register. The holding register addresses are contiguous to facilitate faster polling operations. 9.4 Bit Oriented Code Detector (RBOC) The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194 or in the DS3 C-bit parity far-end Th alarm and control (FEAC) channel. The 64 code (111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel or FEAC channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods. Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones). 9.5 HDLC Receiver (RDLC) The RDLC is a microprocessor peripheral used to receive HDLC frames on the 4kHz ESF facility data link, the E1 Sa-bit data link, the DS3 C-bit parity Path Maintenance Data Link or a specified channel within a T1 or E1 stream. The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS).
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In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes. 9.6 T1 Alarm Integrator (ALMI) The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, or ESF formats. The alarm detection and integration is compatible with the specifications defined in ANSI T1.403 and TR-TSY-000191. The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms ( 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out-of-frame condition and all-ones in the PCM data stream have been present for 1.5 sec (100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec (500 ms). CFA alarm detection algorithms operate in the presence of a 10-3 bit error rate. The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms, 40 ms, and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.
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9.7
Elastic Store (ELST) The Elastic Store (ELST) synchronizes ingress frames to the common ingress clock and frame pulse (CICLK, CIFP) in the Clock Slave ingress modes or to the common ingress H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in H-MVIP modes. The frame data is buffered in a two frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The subsequent ingress frame is deleted. If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The previous ingress frame is repeated. A slip operation is always performed on a frame boundary. When the ingress timing is recovered from the receive data the elastic store can be bypassed to eliminate the 2 frame delay. In this configuration (the Clock Master ingress modes), the elastic store is used to synchronize the ingress frames to the transmit line clock so that per-DS0 loopbacks may be enabled. To allow for the extraction of signaling information in the data channels, superframe identification is also passed through the ELST. For payload conditioning, the ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the ELST is reset. If the data is required to pass through the TECT3 unchanged during an out-offrame condition, then the elastic store may be bypassed.
9.8
Signaling Elastic Stores (RX-SIG-ELST and TX_SIG-ELST) There are two additional elastic stores used to adapt the differences in rate between the CAS or CCS H-MVIP signaling rates and the serial clock and data or SBI data rates when in simultaneous SBI or serial clock and data with
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signaling H-MVIP. These elastic stores are identical to the elastic store described in section 9.7. When simultaneous SBI with CAS or CCS H-MVIP is selected by the SYSOPT[2:0] bits in the Global Configuration register these elastic stores eliminate the need for the H-MVIP interface clock and frame alignment to be externally synchronized to the rate and frame alignment of the individual links carries over the SBI interface. Any rate differences between the H-MVIP interface and an individual link will result in a controlled slip in the CAS or CCS data relative to the data channels of the individual T1 links. When simultaneous serial clock and data with CCS H-MVIP is selected these elastic stores eliminate the need for the H-MVIP interface clock and frame alignment to be externally synchronized to the rate and frame alignment of the individual serial streams. As with simultaneous SBI mode, any rate differences between the H-MVIP interface and an individual link will result in a controlled slip in the CCS signaling relative to the data channels of the individual T1 links. 9.9 Signaling Extractor (SIGX) The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction from an E1 signaling multi-frame or from ESF, and SF T1 formats. In T1 mode, the SIGX block provides signaling bit extraction from the received data stream for ESF and SF framing formats. It selectively debounces the bits, and serializes the results onto the ISIG[x] outputs or CAS bits within the SBI Bus structure. Debouncing is performed on individual signaling bits. This ISIG[x] output is channel aligned with ID[x] output, and the signaling bits are repeated for the entire superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in ESF framing format; in SF format the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel). The SIGX block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 superframes before appearing on the serial output stream. The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
the output signaling for the entire superframe in which the slip occurred; the signaling is unfrozen when the next slip-free superframe occurs. The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling debounce on a per-timeslot basis. The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel basis. 9.10 Receive Per-Channel Serial Controller (RPSC) The RPSC allows data and signaling trunk conditioning to be applied on the ingress stream on a per-channel basis. It also allows per-channel control of data inversion, the extraction of clock and data on ICLK[x] and ID[x] (when the Clock Master: NxChannel mode is active), and the detection or generation of pseudorandom patterns. The RPSC operates on the data after its passage through ELST, so that data and signaling conditioning may overwrite the ELST trouble code. 9.11 Basic Transmitter (XBAS) The T1 Basic Transmitter (XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF or ESF frame formats. In concert with the Transmit Per-Channel Serial Controller (TPSC), the XBAS block, provides per-channel control of idle code substitution, data inversion (either all 8 bits, sign bit magnitude or magnitude only), and zero code suppression. Three types of zero code suppression (GTE, Bell and "jammed bit 8") are supported and selected on a per-channel basis to provide minimum ones density control. An internal signaling control stream provides per-channel control of robbed bit signaling and selection of the signaling source. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning (MTRK) bit in the T1-XBAS Configuration Register. A data link is provided for ESF mode. The data link sources include bit oriented codes and HDLC messages. Support is provided for the transmission of AIS or Yellow alarm signals for all formats. The transmitter can be disabled for framing via the FDIS disable bit in the T1/E1 Transmit Framing and Bypass Options register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the egress stream can be by-passed to the output data stream via the same T1/E1 Transmit
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Framing and Bypass Options register. Finally, the transmitter can be by-passed completely to provide a clear channel operating mode. 9.12 E1 Transmitter (E1-TRAN) The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation. In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning bit in the E1-TRAN Transmit Alarm/Diagnostic Control register. Common Channel Signaling (CCS) is supported in time slot 16 through the Transmit Channel Insertion (TXCI) block. Support is provided for the transmission of AIS and TS16 AIS, and the transmission of remote alarm (RAI) and remote multiframe alarm signals. The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controller, or may be passed transparently from the ED[x] input. 9.13 Transmit Per-Channel Serial Controller (TPSC) The Transmit Per-Channel Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a perchannel basis. It also allows per-channel control of zero code suppression, data inversion, channel loopback (from the ingress stream), channel insertion, and the detection or generation of pseudo-random patterns. The TPSC interfaces directly to the E1-TRAN and T1-XBAS block and provides serial streams for signaling control, idle code data and egress data control. 9.14 Signaling Aligner (SIGA) The Signaling Aligner is a block that is only applicable in T1 operating modes. When enabled, the Signaling Aligner is positioned in the egress path before the T1-XBAS. Its purpose is to ensure that if the signaling on ESIG[x] is changed in the middle of a superframe, the XBAS completes transmitting the A,B,C, and D
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bits for the current superframe before switching to the new values. This permits signaling integrity to be preserved independent of the superframe alignment of the T1-XBAS or the signaling data source. 9.15 Bit Oriented Code Generator (XBOC) The Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link (FDL) channel in ESF framing format, as defined in ANSI T1.403-1989 or in the DS3 C-bit parity Far-End Alarm and Control (FEAC) channel. The 64th code (111111) is similar to the HDLC Flag sequence and is used in the XBOC to disable transmission of any bit oriented codes. When transmission is disabled the FDL or FEAC channel is set to all ones. Bit oriented codes are transmitted on the T1 Facility Data Link or DS3 Far-End Alarm and Control channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. When driving the T1 facility data link the transmitted bit oriented codes have priority over any data transmitted except for ESF Yellow Alarm. The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the last code has been transmitted at least 10 times. An interrupt or polling mechanism is used to determine when the most recent code written the XBOC register is being transmitted and a new code can be accepted. 9.16 HDLC Transmitters (TDPR) The HDLC Transmitter (TDPR) provides a serial data link for the 4 kHz ESF facility data link, E1 Sa-bit data link, the DS3 C-bit parity path maintenance data link or a specified channel within a T1 or E1 stream. The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) may be appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte before transmitting it. The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a
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flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO. The second procedure transmits data only when the FIFO depth has reached a user configured upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences. Abort characters can be continuously transmitted at any time by setting the ABT bit in the TDPR Configuration register. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDRI interrupt. 9.17 T1 Automatic Performance Report Generation (APRM) In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is generated each second for T1 ESF applications. The report conforms to the HDLC protocol and is inserted into the ESF facility data link. The performance report can only be transmitted if the TDPR is configured to insert the ESF Facility Data Link and the PREN bit of the TDPR Configuration register is logic 1. The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted. See the Operation section for details on the performance report encoding.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9.18 Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT) The Digital Jitter Attenuation function is provided by the DJAT blocks. Each framer in the TECT3 contains two separate jitter attenuators, one between the receive demultiplexed or demapped T1 or E1 link and the ingress interface (RJAT) and the other between the egress interface and the transmit T1 or E1 link to be multiplexed into DS3 (TJAT). Each DJAT block receives jittered data and stores the stream in a FIFO timed to the associated receive jittered clock. The jitter attenuated data emerges from the FIFO timed to the jitter attenuated clock. In the RJAT, the jitter attenuated clock (ICLK[x]) is referenced to the demultiplexed tributary receive clock. In the TJAT, the jitter attenuated transmit tributary clock feeding the M13 multiplexer may be referenced to either CTCLK, CECLK, or the tributary receive clock. In T1 mode each jitter attenuator generates its output clock by adaptively dividing the 37.056 MHz XCLK signal according to the phase difference between the jitter attenuated clock and the input reference clock. Jitter fluctuations in the phase of the reference clock are attenuated by the phase-locked loop within each DJAT so that the frequency of the jitter attenuated clock is equal to the average frequency of the reference. To best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 6.6 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 6.6 Hz are tracked by the jitter attenuated clock. The jitter attenuated clock (ICLK[x] for the RJAT and transmit clock for the TJAT) are used to read data out of the FIFO. In E1 mode each jitter attenuator generates the jitter-free 2.048 MHz output clock by adaptively dividing the 49.152 MHz XCLK signal according to the phase difference between the jitter attenuated clock and input reference clock. Fluctuations in the phase of the input data clock are attenuated by the phaselocked loop within DJAT so that the frequency of the jitter attenuated clock is equal to the average frequency of the input data clock. Phase fluctuations with a jitter frequency above 8.8 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 8.8 Hz are tracked by the jitter attenuated clock. To provide a smooth flow of data out of DJAT, the jitter attenuated clock is used to read data out of the FIFO. The TJAT and RJAT have programmable divisors in order to generate the jitter attenuated clock from the various reference sources. The divisors are set using the TJAT and RJAT Jitter Attenuator Divider N1 and N2 registers. The following formula must be met in order to select the values of N1 and N2: Fin/(N1 + 1) = Fout/(N2 + 1)
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where Fin is the input reference clock frequency and Fout is the output jitter attenuated clock frequency. The values on N1 and N2 can range between 1 and 256. Fin ranges from 8KHz to 2.048MHz in 8KHz increments. If the FIFO read pointer comes within one bit of the write pointer, DJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data. Jitter Characteristics Each DJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. In T1 mode each DJAT can accommodate up to 28 UIpp of input jitter at jitter frequencies above 6 Hz. For jitter frequencies below 6 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In E1 mode each DJAT can accommodate up to 35 UIpp of input jitter at jitter frequencies above 9 Hz. For jitter frequencies below 9 Hz, more correctly called wander, the tolerance increases 20 dB per decade. In most applications the each DJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The DJAT blocks meet the stringent low frequency jitter tolerance requirements of AT&T TR 62411, ITU-T Recommendation G.823 and thus allow compliance with this standard and the other less stringent jitter tolerance standards cited in the references. The DJAT exhibits negligible jitter gain for jitter frequencies below 6.6 Hz, and attenuates jitter at frequencies above 6.6 Hz by 20 dB per decade in T1 mode. It exhibits negligible jitter gain for jitter frequencies below 8.8 Hz, and attenuates jitter at frequencies above 8.8 Hz by 20 dB per decade in E1 mode. In most applications the DJAT Blocks will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through DJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of 24X (37.056 MHz or 49.152 MHz) digital phase locked loop for transmit clock generation. DJAT meets the jitter transfer requirements of AT&T TR 62411. The DJAT allows the implied T1 jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met. The DJAT meets the E1 jitter attenuation requirements of the ITU-T Recommendations G.737, G.738, G.739 and G.742.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Jitter Tolerance Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For T1 modes the DJAT input jitter tolerance is 29 Unit Intervals peak-topeak (UIpp) with a worst case frequency offset of 354 Hz. For E1 modes the input jitter tolerance is 35 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 308 Hz. In either mode jitter tolerance is 48 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK divided by 24 and that of the input data clock. Figure 8: DJAT Jitter Tolerance T1 Modes 100 28 Jitter Amplitude, UIpp 10
acceptable DJAT minimum tolerance
29
1.0
unacceptable
0.2
0.1
0.01
1
4.9 10
100
0.3k
1k
10k
100k
Jitter Frequency, Hz
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Figure 9: DJAT Jitter Tolerance E1 Modes
The accuracy of the XCLK frequency and that of the reference clock used to generate the jitter attenuated clock have an effect on the minimum jitter tolerance. Given that the DJAT PLL reference clock accuracy can be 200 Hz from 1.544 MHz or be 103 Hz from 2.048 MHz, and that the XCLK input accuracy can be 100 ppm from 37.056 MHz or 100 ppm from 49.152 MHz, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK / 24 are shown in Figure 10 and Figure 11. An XCLK input accuracy of 100 ppm is only acceptable if an accurate line rate reference is provided. If TJAT is left to free-run without a reference, or referenced to a derivative of XCLK, then XCLK accuracy must be 32 ppm.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 10: DJAT Minimum Jitter Tolerance vs. XCLK Accuracy T1 Modes
40 36 35 DJAT Minimum Jitter Tolerance UI pp 34
30
29
Max frequency offset (PLL Ref to XCLK)
25 100 XCLK Accuracy
200 0
250 32
300
354 100
Hz ppm
Figure 11: DJAT Minimum Jitter Tolerance vs. XCLK Accuracy E1 Modes
45 42.4 40 DJAT Minimum Jitter Tolerance UI pp 39 34.9
35
Max frequency offset (PLL Ref to XCLK) XCLK Accuracy
30 100 0
200 49
300 308 100
Hz ppm
Jitter Transfer The output jitter in T1 mode for jitter frequencies from 0 to 6.6 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 6.6 Hz are attenuated at a level of 6 dB per octave, as shown in Figure 12.
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Figure 12: DJAT Jitter Transfer T1 Modes
0 -10 -20 -30 -40 -50
62411 min DJAT response 62411 max 43802 max
Jitter Gain (dB)
1 6.6
10
100 1k Jitter Frequency, Hz
10k
The output jitter in E1 mode for jitter frequencies from 0 to 8.8 Hz is no more than 0.1 dB greater than the input jitter, excluding the residual jitter. Jitter frequencies above 8.8 Hz are attenuated at a level of 6 dB per octave, as shown in Figure 13. Figure 13: DJAT Jitter Transfer E1 Modes
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Frequency Range In the non-attenuating mode for T1 rates, that is, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (29 UIpp) and maximum XCLK frequency offset ( 100 ppm). The nominal range is 1.544 MHz 963 Hz with no jitter or XCLK frequency offset. In the non-attenuating mode for E1 rates the tracking range is 1.963 to 2.133 MHz. The guaranteed linear operating range for the jittered input clock is 2.048 MHz 1278 Hz with worst case jitter (42 UIpp) and maximum XCLK frequency offset ( 100 ppm). 9.19 Timing Options (TOPS) The Timing Options block provides a means of selecting the source of the internal input clock to the TJAT block, the reference clock for the TJAT digital PLL, and the clock source used to derive the transmit clock to the M13 mux. 9.20 Pseudo Random Binary Sequence Generation and Detection (PRBS) The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software selectable PRBS generator and checker for 211-1, 215-1 or 220-1 PRBS polynomials for use in the T1 and E1 links. PRBS patterns may be generated in either the transmit or receive directions, and detected in the opposite direction. The PRBS block can perform an auto synchronization to the expected PRBS pattern and accumulates the total number of bit errors in two 24-bit counters. The error count accumulates over the interval defined by to the Global PMON Update Register. When an accumulation is forced, the holding register is updated, and the counter reset to begin accumulating for the next interval. The counter is reset in such a way that no events are missed. The data is then available in the Error Count registers until the next accumulation. 9.21 Pseudo Random Pattern Generation and Detection (PRGD) The Pseudo Random Pattern Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer for the DS3 payload. Patterns may be generated in the transmit direction, and detected in the receive direction. Two types of ITU-T O.151 compliant test patterns are provided : pseudo-random and repetitive.
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The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7. The PRGD can be programmed to check for the generated pseudo random pattern. The PRGD can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. The counters accumulate either over intervals defined by writes to the Pattern Detector registers, upon writes to the Global PMON Update Register or automatically once a second. When an accumulation is forced, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next accumulation. 9.22 DS3 Framer (DS3-FRMR) The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications. The DS3-FRMR decodes a B3ZS-encoded signal and provides indications of line code violations. The B3ZS decoding algorithm and the LCV definition can be independently chosen through software. A loss of signal (LOS) defect is also detected for B3ZS encoded streams. LOS is declared when inputs RPOS and RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when the ones density on RPOS and/or RNEG is greater than 33% for 175 1 RCLK cycles. The framing algorithm examines five F-bit candidates simultaneously. When at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. When a single F-bit candidate remains in a set, the first bit in the supposed M-subframe is examined for the M-frame alignment signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing is declared, and out-of-frame is removed, if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. During the examination of the M-bits, the X-bits and P-bits are ignored. The algorithm gives a maximum average reframe time of 1.5 ms. While the DS3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled by the MBDIS bit in the DS3 Framer Configuration register. The 3 out of 8 consecutive F-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive F-bits ratio. Either out-of-frame criteria allows an out-offrame defect to be detected quickly when the M-subframe alignment patterns or, optionally, when the M-frame alignment pattern is lost. Also while in-frame, line code violations, M-bit or F-bit framing bit errors, and Pbit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and far end block errors are indicated. These error indications, as well as the line code violation and excessive zeros indication, are accumulated over 1 second intervals with the Performance Monitor (PMON). Note that the framer is an off-line framer, indicating both OOF and COFA events. Even if an OOF is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the DS3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" M-frame intervals. For the RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE) while valid frame alignment is maintained. This discrepancy threshold ensures the detection algorithms operate in the presence of a 10-3 bit error rate. For AIS, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and the C-bits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). Each "valid" Mframe causes an associated integration counter to increment; "invalid" M-frames cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). RED, AIS, or IDLE are removed when the respective counter decrements to 0. DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is deasserted.
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Valid X-bits are extracted by the DS3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status remains in its previous state. The extracted FERF status is buffered for 2 Mframes before being reported within the DS3 FRMR Status register. This buffer ensures a better than 99.99% chance of freezing the FERF status on a correct value during the occurrence of an out of frame. When the C-bit parity application is enabled, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. Codes in the FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC messages in the Path Maintenance Data Link are received by the Data Link Receiver (RDLC). The DS3-FRMR can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error. The DS3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS3-FRMR. Access to these registers is via a generic microprocessor bus. 9.23 Performance Monitor Accumulator (DS3-PMON) The Performance Monitor (PMON) Block interfaces directly with the DS3 Framer (DS3-FRMR). Saturating counters are used to accumulate: * * * * * * line code violation (LCV) events parity error (PERR) events path parity error (CPERR) events far end block error (FEBE) events excess zeros (EXZS) framing bit error (FERR) events
Due to the off-line nature of the DS3 Framer, PMON continues to accumulate performance meters even while the DS3-FRMR has declared OOF.
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When an accumulation interval is signaled by a write to the PMON register address space, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed. When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval. Whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. 9.24 DS3 Transmitter (DS3-TRAN) The DS3 Transmitter (DS3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats. When configured for the C-bit parity application, all overhead bits are inserted. When configured for the M23 application, all overhead bits except the stuff control bits (the C-bits) are inserted; the C-bits are inserted by the upstream MX23 TSB. Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the DS3-FRMR. A valid pair of P-bits is automatically calculated and inserted by the DS3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted. When enabled for C-bit parity operation, the FEAC channel is sourced by the XBOC bit-oriented code transmitter. The path maintenance data link messages are sourced by the TDPR data link transmitter. The DS3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9.25 M23 Multiplexer (MX23) The M23 Multiplexer (MX23) integrates circuitry required to asynchronously multiplex and demultiplex seven DS2 streams into, and out of, an M23 or C-bit Parity formatted DS3 serial stream. When multiplexing seven DS2 streams into an M23 formatted DS3 stream, the MX23 TSB performs rate adaptation to the DS3 by integral FIFO buffers, controlled by timing circuitry. The C-bits are also generated and inserted by the timing circuitry. Software control is provided to transmit DS2 AIS and DS2 payload loopback requests. The loopback request is coded by inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7). The TSB also supports generation of a C-bit Parity formatted DS3 stream by providing an internally generated DS2 rate clock corresponding to a 100% stuffing ratio. Integrated M13 applications are supported by providing an internally generated DS2 rate clock corresponding to a 39.1% stuffing ratio. When demultiplexing seven DS2 streams from an M23 formatted DS3, the MX23 performs bit destuffing via interpretation of the C-bits. The MX23 also detects and indicates DS2 payload loopback requests encoded in the C-bits. As per ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. DS2 payload loopback can be activated or deactivated under software control. During payload loopback the DS2 stream being looped back still continues unaffected in the demultiplex direction to the DS2 Framer. All seven demultiplexed DS2 streams can also be replaced with AIS on an individual basis under register control or they can be configured to be replaced automatically on detection of out of frame, loss of signal, RED alarm or alarm indication signal. 9.26 DS2 Framer (DS2-FRMR) The FRMR DS2 Framer integrates circuitry required for framing to a DS2 bit stream and is directly compatible with the M12 DS2 application. The FRMR can also be configured to frame to a G.747 bit stream. The DS2 FRMR frames to a DS2 signal with a maximum average reframe time of less than 7 ms and frames to a G.747 signal with a maximum average reframe
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
time of 1 ms. In DS2 mode, both the F-bits and M-bits must be correct for a significant period of time before frame alignment is declared. In G.747 mode, frame alignment is declared if the candidate frame alignment signal has been correct for 3 consecutive frames (in accordance with CCITT Rec. G.747 Section 4). Once in frame, the DS2 FRMR provides indications of the M-frame and Msubframe boundaries, and identifies the overhead bit positions in the incoming DS2 signal or provides indications of the frame boundaries and overhead bit positions in the incoming G.747 signal. Depending on configuration, declaration of DS2 out-of-frame occurs when 2 out of 4 or 2 out of 5 consecutive F-bits are in error (These two ratios are recommended in TR-TSY-000009 Section 4.1.2) or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled via the MBDIS bit in the DS2 Framer configuration register. In G.747 mode, out-of-frame is declared when four consecutive frame alignment signals are incorrectly received (in accordance with CCITT Rec. G.747 Section 4). Note that the DS2 framer is an off-line framer, indicating both OFF and COFA. Error events continue to be indicated even when the FRMR is indicating OOF, based on the previous frame alignment. The RED alarm and alarm indication signal are detected by the DS2 FRMR in 9.9 ms for DS2 format and in 6.9 ms for G.747 format. The framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" DS2 M-frame or G.747 frame intervals. For the RED alarm, a DS2 Mframe (or G.747 frame, depending upon the framing format selected) is said to be a "valid" interval if it contains a RED defect, defined as the occurrence of an OOF event during that M-frame (or G.747 frame). For AIS, a DS2 M-frame (or G.747 frame) is said to be a "valid" interval if it contains AIS, defined as the occurrence of less than 9 zeros while the framer is out of frame during that Mframe (or G.747 frame). The discrepancy threshold ensures the detection algorithm operates in the presence of bit error rates of up to 10-3. Each "valid" DS2 M-frame (or G.747 frame) causes an integration counter to increment; "nonvalid" DS2 M-frame (or G.747 frame) intervals cause a decrement. RED or AIS is declared if the associated integrator count saturates at 53, resulting in a detection time of 9.9 ms for DS2 and 6.9 ms for G.747. RED or AIS declaration is deasserted when the associated count decrements to 0. The DS2 X-bit or G.747 remote alarm indication (RAI) bit is extracted by the DS2 FRMR to provide an indication of far end receive failure. The FERF status is set to the current X/RAI state only if the two successive X/RAI bits were in the same state. The extracted FERF status is buffered for 6 DS2 M-frames or 6 G.747 frames before being reported within the DS2 FRMR Status register. This buffer ensures a virtually 100% probability of freezing the FERF status in a valid state during an out of frame occurrence in DS2 mode, and ensures a better than 99.9% probability of freezing the valid status during an OOF occurrence in G.747
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
mode. When an OOF occurs, the FERF value is held at the state contained in the last buffer location corresponding to the previous sixth M-frame or G.747 frame. This location is not updated until the OOF condition is deasserted. Meanwhile, the last four of the remaining five buffer locations are loaded with the frozen FERF state while the first buffer location corresponding to the current Mframe/ G.747 frame is continually updated every M-frame/G.747 frame based on the above FERF definition. Once correct frame alignment has been found and OOF is deasserted, the first buffer location will contain a valid FERF status and the remaining five buffer locations are enabled to be updated every M-frame or G.747 frame. DS2 M-bit and F-bit framing errors are indicated as are G.747 framing word errors (or bit errors) and G.747 parity errors. These error indications are accumulated for performance monitoring purposes in internal, microprocessor readable counters. The performance monitoring accumulators continue to count error indication even while the framer is indicating OOF. The DS2 FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the DS2 FRMR. 9.27 M12 Multiplexer (MX12) The MX12 M12 Multiplexer integrates circuitry required to asynchronously multiplex and demultiplex four DS1 streams into, and out of, an M12 formatted DS2 serial stream (as defined in ANSI T1.107 Section 7) and to support asynchronous multiplexing and demultiplexing of three 2048 kbit/s into and out of a G.747 formatted 6312 kbit/s high speed signal (as defined in CCITT Rec. G.747). When multiplexing four DS1 streams into an M12 formatted DS2 stream, the MX12 TSB performs logical inversion on the second and fourth tributary streams. Rate adaptation to the DS2 is performed by integral FIFO buffers, controlled by timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of sinusoidal jitter on the DS1 clocks for all jitter frequencies. X, F, M, and C bits are also generated and inserted by the timing circuitry. Software control is provided to transmit Far End Receive Failure (FERF) indications, DS2 AIS, and DS1 payload loopback requests. The loopback request is coded by inverting one of the three C-bits (the default option is compatible with ANSI T1.107a Section 8.2.1 and TR-TSY-000009 Section 3.7).Two diagnostic options are provided to invert the transmitted F or M bits. When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12 performs bit destuffing via interpretation of the C-bits. The MX12 also detects and indicates DS1 payload loopback requests encoded in the C-bits. As per
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7, the loopback command is identified as C3 being the inverse of C1 and C2. Because TR-TSY000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. DS1 payload loopback can be activated or deactivated under software control. During payload loopback the DS1 stream being looped back still continues unaffected in the demultiplex direction. The second and fourth demultiplexed DS1 streams are logically inverted, and all four demultiplexed DS1 streams can be replaced with AIS on an individual basis. Similar functionality supports CCITT Recommendation G.747. The FIFO is still required for rate adaptation. The frame alignment signal and parity bit are generated and inserted by the timing circuitry. Software control is provided to transmit Remote Alarm Indication (RAI), high speed signal AIS, and the reserved bit. A diagnostic option is provided to invert the transmitted frame alignment signal and parity bit. When demultiplexing three 2048 kbit/s streams from a G.747 formatted 6312 kbit/s stream, the MX12 performs bit destuffing via interpretation of the C-bits. Tributary payload loopback can be activated or deactivated under software control. Although no remote loopback request has been defined for G.747, inversion of the third C-bit triggers a loopback request detection indication in anticipation of Recommendation G.747 refinement. All three demultiplexed 2048 kbit/s streams can be replaced with AIS on an individual basis. 9.28 Egress System Interface (ESIF) The Egress System Interface (ESIF) block provides system side serial clock and data access as well as H-MVIP access for up to 28 T1 or 21 E1 transmit streams. There are several master and slave clocking modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192Mb/s H-MVIP there are three separate interfaces for data, CAS signaling and CCS signaling. The H-MVIP signaling interfaces can be used in combination with the serial clock and data and SBI interface in certain applications. Control of the system side interface is global to TECT3 and is selected through the SYSOPT[2:0] bits in the Global Configuration register at address 0001H. The system interface options are serial clock and data, H-MVIP, SBI bus, SBI bus with CAS or CCS H-MVIP and serial clock and data with CCS H-MVIP. Two Clock Master modes provide a serial clock and data egress interface with per link clocking provided by TECT3. The clock master modes are Clock Master:
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
NxChannel and Clock Master: Clear Channel. Four Clock slave modes provide three serial clock and data egress interfaces and a H-MVIP interface all with externally sourced clocking. The slave modes are Clock Slave: EFP Enabled, Clock Slave: External Signaling, Clock Slave: Clear Channel and Clock Slave: HMVIP. The egress serial clock and data interface clocking modes are selected via the EMODE[2:0] bits in the T1/E1 Egress Serial Interface Mode Select register. In all egress Clock Master modes the transmit clock can be sourced from either the common transmit clock, CTCLK, one of the two recovered clocks, RECVCLK1 and RECVCLK2, or the received clock for that link. The selection between CTCLK, RECVCLK1 and RECVCLK2 as the reference transmit clock is the same for all T1/E1 framers. Jitter attenuation can be applied to all master mode clocks with the TJAT. Figure 14: Clock Master: NxChannel
C TC LK Receive C LK[1:28]
ED[1:28] EC LK[1:28]
ED[x] Tim ed to ECLK[x]
ESIF Egress System Interface
T1-XB AS/E1-TR AN BasicTransm itte r: Frame G eneration, Alarm Insertio n, Signaling Insertion, Trunk C onditioning Line C oding
TJAT Digital PLL
Transmit C LK[1:28]
Transmit D ata[1:28]
TRANSMITTER
Clock Master: NxChannel mode does not indicate frame alignment to the upstream device. Instead, ECLK[x] is gapped on a per channel basis so that a subset of the 24 channels in a T1 frame or 32 channels in an E1 frame are inserted on ED[x]. Channel insertion is controlled by the IDLE_CHAN bits in the TPSC block's Egress Control Bytes. The framing bit position is always gapped, so the number of ECLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-channel basis. The parity functions should not be enabled in NxChannel mode.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 15: Clock Master: Clear Channel
C TCLK Receive CLK[1:28]
ED[1:28] EC LK[1:28]
ED[x] Tim ed to ECLK[x]
ESIF Egress System Inte rface
TJAT Digital PLL
Transmit C LK[1 :28]
Transmit D ata[1 :28]
TRANSMITTER
Clock Master: Clear Channel mode has no frame alignment therefore no frame alignment is indicated to the upstream device. ECLK[x] is a continuous clock at 1.544Mb/s for T1 links or 2.048Mb/s for E1 links. Figure 16: Clock Slave: EFP Enabled
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding
ED[1:28] EFP[1:28] CEFP CECLK
ESIF Egress System Inte rface
TJAT Digital PLL TJAT FIFO
Transmit C LK[1 :28]
Transmit D ata[1:28]
Inputs Tim ed to CEC LK
In Clock Slave: EFP Enabled mode, the egress interface is clocked by the common egress clock, CECLK. The transmitter is either frame-aligned or superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP bit in the Master Egress Slave Mode Serial Interface Configuration register. EFP[x] is configurable to indicate the frame alignment or the superframe alignment of ED[x]. CECLK can be enabled to be either a 1.544 MHz clock for T1 links or a 2.048 MHz clock for T1 and E1 links. The CECLK2M bit in the Master Egress Slave Mode Serial Interface Configuration register selects the 2.048MHz clock for T1 operation.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 17: Clock Slave: External Signaling
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding
ED[1:28] ESIG[1:28 ] CEFP CECLK
ESIF Egress System Inte rface
TJAT Digital PLL TJAT FIFO
Transmit C LK[1 :28]
Transmit D ata[1:28]
Inputs Tim ed to CEC LK
In Clock Slave: External Signaling mode, the egress interface is clocked by the common egress clock, CECLK. The transmitter is either frame-aligned or superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP bit in the Master Egress Slave Mode Serial Interface Configuration register. The ESIG[x] signal contains the robbed-bit signaling data to be inserted into Transmit Data[x], with the four least significant bits of each channel on ESIG[x] representing the signaling state (ABCD or ABAB in T1 SF mode). EFP[x] is not available in this mode. Figure 18: Clock Slave: Clear Channel
TRANSMITTER
ED[1:28]
ESIF Egress System Inte rface
TJAT Digital PLL TJAT FIFO
Transmit C LK[1 :28]
ECLK[1:28]
Transmit D ata[1:28]
Input Tim ed to ECLK[x]
In Clock Slave: Clear Channel mode, the egress interface is clocked by the externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are bypassed except for the TJAT which may or may not be bypassed depending on the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options register. Typically the TJAT would be bypassed unless jitter attenuation is required on ECLK[x].
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 19: Clock Slave: H-MVIP
TRANSMITTER
MVED [1:7] CASED[1:7] CC SED CMVFP C MVFPC C MV8MCLK ESIF Egress System Inte rface T1-XB AS/E1-TRAN BasicTransm itter: Frame Gene ration, Alarm Insertion, Signaling Insertion, Trunk Co nditioning Line Coding TJAT Digital PLL TJAT FIFO Transmit C LK[1:28]
Transmit D ata[1:28]
Inputs Tim ed to CMV8MC LK
When Clock Slave: H-MVIP mode is enabled a 8.192Mb/s H-MVIP egress interface multiplexes up to 672 channels from 28 T1s or 21 E1s, up to 672 channel associated signaling (CAS) channels from 28 T1s or 21 E1s and common channel signaling from up to 28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. Seven H-MVIP data signals, MVED[1:7], share pins with serial PCM data inputs, ED[x], to provide H-MVIP access for up to 672 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192Mb/s H-MVIP signal. The multiplexed data input is shared with the lowest numbered T1 or E1 serial PCM link in the bundle, for example MVED[2] combines the DS0s or timeslots of ED[5,6,7,8] and is pin multiplexed with ED[5]. This mode is selected when the SYSOPT[2:0] bits in the Global Configuration register are set to H-MVIP. A separate seven signal H-MVIP interface is for access to the channel associated signaling for 672 channels. The CAS H-MVIP interface is time division multiplexed exactly the same way as the data channels. The CAS HMVIP is synchronized with the H-MVIP data channels when SYSOPT[2:0] is set to H-MVIP mode. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in parallel with each data byte. The egress CAS HMVIP interface, CASED[1:7], is multiplexed with seven serial PCM egress data pins, ED[2,6,10,14,18,22,26]. The CAS H-MVIP interface can be used in parallel with the SBI Add bus as an alternative method for accessing the CAS bits while data transfer occurs over the SBI bus. This is selected when the SYSOPT[2:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface" and the ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set to 0.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
A separate H-MVIP interface consisting of a single signal is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSED, is not multiplexed with any other pins. CCSED can be used in parallel with the Clock Slave:H-MVIP mode when SYSOPT[2:0] is set to "H-MVIP Interface" and the ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set to 1, a Clock Slave serial interface when SYSOPT[2:0] is set to "Serial Clock and Data Interface with CCS H-MVIP Interface", or the SBI Add bus when SYSOPT[2:0] is set to "SBI Interface with CAS or CCS H-MVIP Interface" and the ECCSEN bit is set to 1. The V5 channels in E1 mode can also be enabled over CCSEN when the ETS15EN and ETS31EN bits in the T1/E1 Egress Serial Interface Mode Select register are set to 1. When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a transmit signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. Figure 20: Clock Master: Serial Data and H-MVIP CCS
TRANSMITTER
ED[1:28] EFP[1:28] ICLK[1:28]
ED[x] Inputs Timed to ICLK[x]
CCSED CMVFP CMVFPC CMV8MCLK
ESIF Egress System Interface
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Insertion, Trunk Conditioning Line Coding
TJAT Digital PLL TJAT FIFO
Transmit CLK[1:28]
Transmit Data[1:28]
Inputs Timed to CMV8MCLK
When Clock Master: Serial Data and H-MVIP CCS mode is enabled, payload data may be sourced through the egress serial interface, while common channel signaling is sourced in parallel through the H-MVIP interface. The H-MVIP egress interface multiplexes common channel signaling from up to 28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. Common channel signaling over H-MVIP uses a Clock Slave serial interface, selected when SYSOPT[2:0] is set to "Serial Clock and Data Interface with CCS H-MVIP Interface". CCSED is a single dedicated input pin sampled by CMV8MCLK, used to time division multiplex the common channel signaling (CCS) for all T1s
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
and E1s and additionally the V5 channels in E1 mode. The V5 channels in E1 mode can also be enabled over CCSED when the ETS15EN and ETS31EN bits in the T1/E1 Egress Serial Interface Mode Select register are set to 1. The ingress clock, ICLK[x], is a 1.544MHz or 2.048MHz clock generated from the 16.384MHz CMV8MCLK. (Note that in T1 mode, this clock does not divide down to T1 rate evenly, resulting in a gappy clock. The minimum period is 10 times that of CMV8MCLK.) ICLK[x] is pulsed for each bit in the 193 bit T1 or 256 bit E1 frame (i.e. NxDS0 controls are not applicable in this mode). Payload data on ID[x] is output relative to this clock. The ingress frame alignment is indicated by TECT3 on IFP[x], again timed to ICLK[x]. Note that several of the serial PCM egress data pins ED[x] are multiplexed with the egress data H-MVIP data interface. ED[1,5,9,13,17,21,25] share pins with the H-MVIP data signals MVED[1:7]. ED[2,6,10,14,18,22,26] share pins with the H-MVIP CAS signals CASED[1:7]. 9.29 Ingress System Interface (ISIF) The Ingress System Interface (ISIF) block provides system side serial clock and data access as well as H-MVIP access for up to 28 T1 or 21 E1 receive streams. There are several master and slave clock modes for serial clock and data system side access to the T1 and E1 streams. When enabled for 8.192Mb/s H-MVIP there are three separate interfaces for data and signaling. The H-MVIP signaling interfaces can be used in combination with the serial clock and data and SBI interface in certain applications. Control of the system side interface is global to TECT3 and is selected through the SYSOPT[2:0] bits in the Global Configuration register at address 0001H. The system interface options are serial clock and data, H-MVIP, SBI bus, SBI bus with CAS or CCS H-MVIP and serial clock and data with CCS H-MVIP. Three Clock Master modes provide a serial clock and data ingress interface with clocking provided by TECT3. The clock master modes are Clock Master: Full T1/E1, Clock Master : NxChannel, Clock Master: Clear Channel. Two Clock slave modes provide two serial clock and data ingress interfaces and a H-MVIP interface. All Clock slave modes accept externally sourced clocking. The clock slave modes are: Clock Slave: External Signaling or Clock Slave: H-MVIP. The ingress serial clock and data interface clocking modes are selected via the IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. Clock Master: NxChannel and Clock Master: Full T1/E1 use the same IMODE[1:0] selection and are differentiated by the INXCHAN[1:0] bits in the same ragister as IMODE[1:0].
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 21: Clock Master: Full T1/E1
ID[1 :28] IFP [1:28]
ID[x], IFP[x] Tim ed to ICLK [1:28]
ISIF Ingress System Interface
FRAM Framer: Slip Bu ffer RA M FRM R Framer: Frame A lignmen t, Alarm Extraction
RECEIVER
RJAT Digital Jitter Attenuator
Receive Data[1:28] Receive CLK[1:28]
ICLK[1:28]
In Clock Master: Full T1/E1 mode, the elastic store is bypassed and the ingress clock (ICLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock coming from the M13 multiplex. Jitter attenuation is selectable by the RJATBYP bit in the T1/E1 Receive Options register. ICLK[x] is pulsed for each bit in the 193 bit T1 or 256 bit E1 frame. The ingress data appears on ID[x] and the ingress frame alignment is indicated by IFP[x]. In this mode, demultiplexed T1 or E1 data passes through the TECT3 unchanged during outof-frame conditions, similar to an offline framer system. When the TECT3 is the clock master in the ingress direction, the elastic store is used to buffer between the ingress and egress clocks to facilitate per-Channel loopback. Figure 22: Clock Master: NxChannel
ID[1 :28] IFP [1:28] ICLK[1:28]
ID[x], IFP[x] Tim ed to gapped ICLK [1:28]
ISIF Ingress System Inte rface
FRAM Framer: Slip Bu ffer RA M FRM R Framer: Frame A lignmen t, Alarm Extraction
RECEIVER
RJAT Digita l Jitter Attenuator
Receive Data[1:28] Receive CLK[1:28]
In Clock Master: NxChannel mode, ICLK[x] is a gapped version of the jitter attenuated 1.544 MHz or 2.048 MHz receive clock coming from the M13 multiplex. ICLK[x] is gapped on a per channel basis so that a subset of the 24 channels in the T1 frame or 32 channels in an E1 frame is extracted on ID[x]. IFP[x] indicates frame alignment but has no clock since it is gapped during the framing bits. Channel extraction is controlled by the RPSC block. The framing bit position is always gapped, so the number of ICLK[x] pulses is controllable from 0 to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-channel basis. In this mode, demultiplexed or demapped T1 or E1 streams pass through
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
the TECT3 unchanged during out-of-frame conditions. The parity functions are not usable in NxChannel mode. When the TECT3 is the clock master in the ingress direction, the elastic store is used to buffer between the ingress and egress clocks to facilitate per-Channel loopback. Figure 23: Clock Master: Clear Channel
ID[x]Timed to IC LK [x]
RECEIVER
ISI F Ingress Syst em Inte rfac e
ID[1 :28] ICLK[ 1:28]
RJAT Digita l Jitter Attenuator
Receive Data[1:28] Receive CLK[1:28]
In Clock Master: Clear Channel mode, the elastic store is bypassed and the ingress clock (ICLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048 MHz receive clock coming from the M13 multiplex. The ingress data appears on ID[x] which no frame alignment indication. Per channel loopbacks are not available in Clear channel mode. The RCVCLRCH mode bit in the T1/E1 Receive Options register must be set to 1 in Clock master: Clear Channel mode. Figure 24: Clock Slave: External Signaling
CICLK CIFP ELST Elastic Store
FRAM Framer: Slip Buffer RA M FRM R Framer: Frame Alignment, Alarm Extraction
RECEIVER
ID[1 :28] IFP [1:28] ISIG[1:28 ]
ID[x], IFP[x], ISIG[x] Tim ed to CICLK
ISIF Ingress System Inte rface
RJAT Digital Jitter Attenuator
Receive Data[1:28] Receive CLK[1:28]
In Clock Slave: External Signaling mode, the elastic store is enabled to permit CICLK to specify the ingress-side timing. The ingress data on ID[x] and signaling ISIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz common ingress clock (CICLK) and are frame aligned to the common ingress frame pulse (CIFP). CICLK can be enabled to be a 1.544 MHz clock or a 2.048 MHz clock. ISIG[x] contains the robbed-bit signaling state (ABCD or ABAB) in the lower four bits of each channel. IFP[x] indicates either the frame or superframe alignment on ID[x].
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 25: Clock Slave: H-MVIP
RECEIVER
FRAM Framer: Slip Bu ffer RA M FRMR Framer: Frame A lignmen t, Alarm Ext raction RJAT Digita l Jitter Attenuator Receive Data[1:28] Receive CLK[1:28]
MVID[1 :7] CASID [1:7] CCSID CMVFP CMVFPC CMV8MCLK
Inp ut s Ti me d to C M V8 MC LK
ELST Elas tic Store ISI F Ingress Syst em Inte rfac e
When Clock Slave: H-MVIP mode is enabled a 8.192Mb/s H-MVIP ingress interface multiplexes up to 672 channels from 28 T1s or 21 E1s, up to 672 channel associated signaling (CAS) channels from 28 T1s or 21 E1s and common channel signaling (CCS) from up to 28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. The three ingress H-MVIP interfaces operate independently except that using any one of these forces the T1 or E1 framer to operate in synchronous mode, meaning that elastic stores are used. Seven H-MVIP data signals, MVID[1:7], share pins with serial PCM data outputs, ID[x], to provide H-MVIP access for up to 672 data channels. The H-MVIP mapping is fixed such that each group of four nearest neighbor T1 or E1 links make up the individual 8.192Mb/s H-MVIP signal. The multiplexed data input is shared with the lowest numbered T1 or E1 serial PCM link in the bundle, for example MViD[2] combines the DS0s or timeslots of ID[5,6,7,8] and is pin multiplexed with ID[5]. This mode is selected when the SYSOPT[2:0] bits in the Global Configuration register are set to H-MVIP. A separate H-MVIP interface consisting of seven pins is for access to the channel associated signaling for all of the 672 data channels. The CAS is time division multiplexed exactly the same way as the data channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each CAS nibble (ABCD bits) out to a full byte in synchronization with each data byte. The ingress CAS H-MVIP interface, CASID[1:7], is multiplexed with seven serial PCM ingress data pins, ID[2,6,10,14,18,22,26]. The CAS H-MVIP interface can be used in parallel with the SBI Drop bus as an alternative method for accessing the CAS bits while data transfer occurs over the
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
SBI bus. This is selected when the SYSOPT[2:0] bits in the Global Configuration register are set to "SBI Interface with CAS or CCS H-MVIP Interface" and the ICCSSEL bit in the T1/E1 Ingress Serial Interface Mode Select register is set to 0. A separate H-MVIP interface consisting of a single signal is used to time division multiplex the common channel signaling (CCS) for all T1s and E1s and additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSID, is not multiplexed with any other pins. CCSID can be used in parallel with the Clock Slave:H-MVIP mode when SYSOPT[2:0] is set to "H-MVIP Interface" and the ICCSSEL bit in the T1/E1 Ingress Serial Interface Mode Select register is set to 1, a Clock Slave serial interface when SYSOPT[2:0] is set to "Serial Clock and Data Interface with CCS H-MVIP Interface", or the SBI Add bus when SYSOPT[2:0] is set to "SBI Interface with CAS or CCS H-MVIP Interface" and the ICCSSEL bit is set to 1. When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with serial clock and data or SBI interfaces a receive signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. Figure 26: Clock Slave: Serial Data and H-MVIP CCS
ID[1:28] IFP[1:28] ICLK[1:28]
RECEIVER
Outputs Timed to ICLK[x]
ELST Elastic Store ISIF Ingress System Interface
FRAM Framer: Slip Buffer RAM FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator
Receive Data[1:28] Receive CLK[1:28]
CCSID CMVFP CMVFPC CMV8MCLK
Inputs Timed to CMV8MCLK
When Clock Slave: H-MVIP mode is enabled, payload data may be extracted throught the ingress serial interface, while common channel signaling is extracted in parallel through the H-MVIP interface. The H-MVIP ingress interface multiplexes common channel signalling from up to 28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for synchronization. Common channel signaling over H-MVIP uses a Clock Slave serial interface, selected when
PROPRIETARY AND CONFIDENTIAL
95
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
SYSOPT[2:0] is set to "Serial Clock and Data Interface with CCS H-MVIP Interface". CCSID is a singal dedicated output pin, output relative to CMV8MCLK, used to time division multiplex the common channel signaling (CCS) for all T1s and E1s, and additionally the V5 channels in E1 mode. The ingress clock, ICLK[x], is a 1.544MHz or 2.048MHz clock generated from the 16.384MHz CMV8MCLK. (Note that in T1 mode, this clock does not divide down to T1 rate evenly, resulting in a gappy clock. The minimum period is 10 times that of CMV8MCLK.) ICLK[x] is pulsed for each bit in the 193 bit T1 or 256 bit E1 frame (i.e. NxDS0 controls are not applicable in this mode). Payload data on ED[x] is sampled by this clock. The egress frame alignment is indicated by TECT3 on EFP[x], again timed to ICLK[x]. Note that several of the serial PMC ingress data pins ID[x] are multiplexed with the ingress data H-MVIP interface. ID[1,5,9,13,17,21,25] share pins with the HMVIP data signals MVID[1:7]. ID[2,6,10,14,18,22,26] share pins with the H-MVIP CAS signals CASID[1:7]. Note also that in this mode, a receive signaling elastic store is used to adapt any timing differences between the data interface and the CCS H-MVIP interface. 9.30 Extract Scaleable Bandwidth Interconnect (EXSBI) The Extract Scaleable Bandwidth Interconnect block demaps up to 28 1.544Mb/s links or a single 44.736Mb/s link from the SBI shared bus. The 1.544Mb/s links can be unframed when used in a straight multiplexer application, or they can be T1 framed and channelized for insertion into the DS3 multiplex. The 44.736Mb/s link can be DS3 unchannelized when the TECT3 is used as a DS3 framer. All egress links extracted from the SBI bus can be timed from the source or from the TECT3. When Timing is from the source the EXSBI commands the PISO to generate 1.544Mb/s or 44.736Mb/s clocks slaved to the arrival rate of the data or from timing link rate adjustments provided from the source and carried with the links over the SBI bus. The 1.544Mb/s clock is synthesized from the 19.44MHz reference clock, SREFCLK, by dividing the clock by either 12 or 13 in a fixed sequence that produces the nominal 1.544Mb/s rate. Timing adjustments are made over 500uS intervals and are done by either advancing or retarding the phase or by adding or deleting a whole 1.544Mb/s clock cycle over the 500uS period. The 44.736Mb/s clock is synthesized from the 51.84MHz or 44.928MHz reference clock, CLK52M. Using either reference clock frequency, the 44.736Mb/s rate is generated by gapping the reference clock in a fixed way. Timing adjustments are performed by adding or deleting four clocks over the 500uS period.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
When the TECT3 is the SBI egress clock master for a link, clocks are sourced within the TECT3. Based on buffer fill levels, the EXSBI sends link rate adjustment commands to the link source indicating that it should send one additional or one fewer bytes of data during the next 500uS interval. Failure of the source to respond to these commands will ultimately result in overflows or underflows which can be configured to generate per link interrupts. Channelized T1s extracted from the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s, but only if the SBI interface is configured for synchronous mode operation. Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI interface. The E1 mode of operation is restricted to using the serial clock and data or H-MVIP system interfaces. 9.31 Insert Scaleable Bandwidth Interconnect (INSBI) The Insert Scaleable Bandwidth Interconnect block maps up to 28 1.544Mb/s links or a single 44.736Mb/s link into the SBI shared bus. The 1.544Mb/s links can be unframed when sourced directly from the DS3 multiplexer, or they can be T1 channelized when sourced by the T1 framers. The 44.736Mb/s link can also be unframed when sourced directly from the DS3 interface. The 44.736Mb/s link can be an unchannelized DS3 when sourced from the DS3 framer. Links inserted into the SBI bus can be timed from the TECT3 or from the far end. The INSBI makes link rate adjustments by adding or deleting an extra byte of data over a 500uS interval based on buffer fill levels. Timing adjustments made by the INSBI are detected by the receiving SBI interface by explicit signals in the SBI bus structure. The INSBI optionally sends link rate information across the SBI bus. This information is used by the receiving SBI interface to create a recovered link clock which is based on small clock phase adjustments signaled by the INSBI. Channelized T1s inserted into the SBI bus optionally have the channel associated signaling (CAS) bits explicitly defined and carried in parallel with the DS0s or timeslots, but only if the SBI interface is configured for synchronous mode operation. When enabled for CAS insertion the INSBI takes a byte serial stream of CAS bits from the SBISIPO and inserts them into the SBI bus structure. Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI interface. The E1 mode of operation is restricted to using the serial clock and data or H-MVIP system interfaces.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9.32 Scaleable Bandwidth Interconnect PISO (SBIPISO) The Scaleable Bandwidth Interconnect Parallel to Serial converter (SBIPISO) generates up to 28 T1s or a DS3 serial clock and data signals from the byte serial stream provided by the Extract SBI block. The generated clock rate can be controlled with commands from the EXSBI. In clock slave mode the generated clock will be increased or decreased in small increments based on FIFO fill levels within the EXSBI or directly with clock rate commands from the far end device who is mastering the clock across the SBI bus. In clock master mode the SBIPISO controls the bit rate by accepting data from the EXSBI at the rate of the individual T1 or DS3 clocks sourced into it. In addition the SBIPISO generates serial CAS signaling streams, frame pulses and multiframe pulses for all T1s and DS3. 9.33 Scaleable Bandwidth Interconnect SIPO (SBISIPO) The Scaleable Bandwidth Interconnect Serial to Parallel converter (SBISIPO) sinks up to 28 T1s or a DS3 serial clock and data signals and generates a byte serial stream to the Insert SBI block. The SBISIPO measures the serial clock against the SBI reference clock and sends this information to the INSBI block and in turn across the SBI bus to the clock generation slave, SBIPISO. In this way an accurate representation of the input clock rate is communicated across the SBI bus. In addition the SBISIPO generates byte serial streams from serial CAS signaling signals, frame pulses and multiframe pulses for all T1s and DS3. 9.34 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The TECT3 identification code is 383150CD hexadecimal. 9.35 Microprocessor Interface The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the Microprocessor Interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the TECT3. The Register Memory Map in Table 2 shows where the normal mode registers are accessed. The registers are organized so that backward software
PROPRIETARY AND CONFIDENTIAL
98
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
compatibility with existing PMC devices is optimized. The resulting register organization splits into sections: Master configuration registers, 28 sets of T1/E1 Framer registers, DS3 M13 multiplexing registers and SBI registers. On power up reset the TECT3 defaults to 28 T1 framers multiplexed into the M13 multiplexer using the DS3 M23 multiplex format. For proper operation some register configuration is necessary. System side access defaults to the SBI bus without any tributaries enabled which will leave the SBI Drop bus tristated. By default interrupts will not be enabled, automatic alarm generation is disabled, a dual rail DS3 LIU interface is expected and an external transmit reference clock is required. Table 2: Register Memory Map Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H000FH 00010H 0011H 0012H 0013H 0014H 0015H001FH 0020H 0021H Register Global Reset Global Configuration Revision/Global PMON Update Master Recovered Clock#1/Reference Clock Select Recovered Clock#2 Select Master Common Egress Serial and H-MVIP Interface Configuration Master Common Ingress Serial and H-MVIP Interface Configuration Reserved Master Clock Monitor #1 Master Clock Monitor #2 Master Clock Monitor #3 Master Clock Monitor #4 Master Clock Monitor #5 Reserved Master Interrupt Source Master Interrupt Status T1/E1 #1-8
PROPRIETARY AND CONFIDENTIAL
99
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0022H 0023H 0024H 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H007FH 0080H00FFH 0080H 0081H 0082H 0083H 0084H 0085H 0086H 0087H 0088H 0089H 008AH
Register Master Interrupt Status T1/E1 #9-16 Master Interrupt Status T1/E1 #17-24 Master Interrupt Status T1 #25-28 Reserved Master Interrupt Status Source SBI Reserved Master Interrupt Status DS3 Master Interrupt Status DS2 Master Interrupt Status MX12 Reserved Master SBIDET0 Collision Detect LSB Master SBIDET0 Collision Detect MSB Master SBIDET1 Collision Detect LSB Master SBIDET1 Collision Detect MSB Reserved T1/E1 Framer Slice #1 T1/E1 Master Configuration Reserved T1/E1 Receive Options T1/E1 Alarm Configuration T1/E1 Egress Line Interface Configuration T1/E1 Master Ingress Serial Interface Mode Select T1/E1 Master Egress Serial Interface Mode Select T1/E1 Master Ingress Parity and Alarm Enable T1/E1 Master Egress Parity Enable T1/E1 Master Serial Interface Configuration T1/E1 Transmit Framing and Bypass Options
PROPRIETARY AND CONFIDENTIAL
100
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 008BH 008CH 008DH 008EH 008FH 0090H 0091H 0092H 0093H 0094H 0095H 0096H 0097H 0098H 0099H 009AH 009BH 009CH 009DH 009EH009FH 00A0H 00A1H 00A2H00A7H 00A8H 00A9H 00AAH00AFH
Register T1/E1 Interrupt Source #1 T1/E1 Interrupt Source #2 T1/E1 Diagnostics T1/E1 PRBS Positioning and HDLC Control Reserved RJAT Interrupt Status RJAT Reference Clock Divisor N1 Control RJAT Output Clock Divisor N2 Control RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor N1 Control TJAT Output Clock Divisor N2 Control TJAT Configuration RX-ELST Configuration RX-ELST Interrupt Enable/Status RX-ELST Idle Code RX-ELST Reserved TX-ELST Configuration TX-ELST Interrupt Enable/Status TX-ELST Reserved RXCE Ingress Data Link Control RXCE Ingress Data Link Bit Select RXCE Reserved TXCI Egress Data Link Control TXCI Egress Data Link Bit Select TXCI Reserved
PROPRIETARY AND CONFIDENTIAL
101
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 00B0H 00B1H 00B2H 00B3H 00B4H 00B5H 00B6H 00B7H 00B8H 00B9H 00BAH 00BBH 00BCH 00BDH 00BEH 00BFH 00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C6H00C7H 00C8H 00C9H 00CAH 00CBH
Register RPSC Configuration RPSC P Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer TPSC Configuration TPSC P Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer PMON Interrupt Enable/Status PMON Framing Bit Error Count PMON OOF/COFA/Far End Block Error Count (LSB) PMON OOF/COFA/Far End Block Error Count (MSB) PMON Bit Error/CRCE Count (LSB) PMON Bit Error/CRCE Count (MSB) PMON Reserved PMON Reserved RDLC Configuration RDLC Interrupt Control RDLC Status RDLC Data RDLC Primary Address Match RDLC Secondary Address Match Reserved TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Transmit Threshold TDPR Interrupt Enable
PROPRIETARY AND CONFIDENTIAL
102
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 00CCH 00CDH 00CEH00CFH 00D0H 00D1H 00D2H 00D3H 00D4H 00D5H 00D6H 00D7H 00D8H 00D9H 00DAH 00DBH 00DCH 00DDH 00DEH 00DFH 00E0H 00E1H 00E2H 00E3H 00E4H 00E5H 00E6H
Register TDPR Interrupt Status/UDR Clear TDPR Transmit Data Reserved PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status PRBS Pattern Select PRBS Reserved PRBS Error Count Register #1 PRBS Error Count Register #2 PRBS Error Count Register #3 PRBS Reserved SIGX Configuration/Change of Signaling State SIGX Channel Indirect Status/Change of Signaling State SIGX Channel Indirect Address/Control/ Change of Signaling State SIGX Channel Indirect Data Buffer/Change of Signaling State RX-SIG-ELST Configuration RX- SIG-ELST Interrupt Enable/Status RX- SIG-ELST Idle Code RX- SIG-ELST Reserved T1 ALMI Configuration T1 ALMI Interrupt Enable T1 ALMI Interrupt Status T1 ALMI Alarm Detection Status T1 XBOC Control T1 XBOC Code T1 RBOC Enable
PROPRIETARY AND CONFIDENTIAL
103
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 00E7H 00E8H 00E9H 00EAH00EBH 00ECH 00EDH 00EEH 00EFH 00F0H 00F1H 00F2H 00F3H 00F4H 00F5H 00F6H 00F7H 00E0H 00E1H 00E2H 00E3H 00E4H 00E5H 00E6H 00E7H 00E8H 00E9H 00EAH
Register T1 RBOC Code Status T1 XBAS Configuration T1 XBAS Alarm Transmit T1 XBAS Reserved T1 FRMR Configuration T1 FRMR Interrupt Enable T1 FRMR Interrupt Status T1 FRMR Reserved T1 APRM Configuration/Control T1 APRM Manual Load T1 APRM Interrupt Status T1 APRM One Second Content Octet 2 T1 APRM One Second Content Octet 3 T1 APRM One Second Content Octet 4 T1 APRM One Second Content MSB (Octet 5) T1 APRM One Second Content LSB (Octet 6) E1 FRMR Frame Alignment Options E1 FRMR Maintenance Mode Options E1 FRMR Framing Status Interrupt Enable E1 FRMR Maintenance/Alarm Status Interrupt Enable E1 FRMR Framing Status Interrupt Indication E1 FRMR Maintenance/Alarm Status Interrupt Indication E1 FRMR Framing Status E1 FRMR Maintenance/Alarm Status E1 FRMR International/National Bits E1 FRMR CRC Error Count - LSB E1 FRMR CRC Error Count - MSB
PROPRIETARY AND CONFIDENTIAL
104
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 00EBH 00ECH 00EDH 00EEH 00EFH 00F0H 00F1H 00F2H 00F3H 00F4H 00F5H 00F6H 00F7H 00F8H00FFH 0100H017FH 0180H01FFH 0200H027FH 0280H02FFH 0300H037FH 0380H03FFH 0400H047FH 0480H04FFH
Register E1 FRMR National Bit Codeword Interrupt Enables E1 FRMR National Bit Codeword Interrupts E1 FRMR National Bit Codewords E1 FRMR Frame Pulse/Alarm Interrupt Enables E1 FRMR Frame Pulse/Alarm Interrupt E1 TRAN Configuration E1 TRAN Transmit Alarm/Diagnostic Control E1 TRAN International Control E1 TRAN Extra Bits Control E1 TRAN Interrupt Enable E1 TRAN Interrupt Status E1 TRAN National Bit Codeword Select E1 TRAN National Bit Codeword Reserved T1/E1 Framer Slice #2 T1/E1 Framer Slice #3 T1/E1 Framer Slice #4 T1/E1 Framer Slice #5 T1/E1 Framer Slice #6 T1/E1 Framer Slice #7 T1/E1 Framer Slice #8 T1/E1 Framer Slice #9
PROPRIETARY AND CONFIDENTIAL
105
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0500H057FH 0580H05FFH 0600H067FH 0680H06FFH 0700H077FH 0780H07FFH 0800H087FH 0880H08FFH 0900H097FH 0980H09FFH 0A00H0A7FH 0A80H0AFFH 0B00H0B7FH 0B00H 0B01H 0B02H 0B03H 0B04H 0B05H
Register T1/E1 Framer Slice #10 T1/E1 Framer Slice #11 T1/E1 Framer Slice #12 T1/E1 Framer Slice #13 T1/E1 Framer Slice #14 T1/E1 Framer Slice #15 T1/E1 Framer Slice #16 T1/E1 Framer Slice #17 T1/E1 Framer Slice #18 T1/E1 Framer Slice #19 T1/E1 Framer Slice #20 T1/E1 Framer Slice #21 T1 Framer Slice #22 T1/E1 Master Configuration Reserved T1/E1 Receive Options T1/E1 Ingress Line Interface Configuration T1/E1 Egress Line Interface Configuration T1/E1 Master Ingress Serial Interface Mode Select
PROPRIETARY AND CONFIDENTIAL
106
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0B06H 0B07H 0B08H 0B09H 0B0AH 0B0BH 0B0CH 0B0DH 0B0EH 0B0FH 0B10H 0B11H 0B12H 0B13H 0B14H 0B15H 0B16H 0B17H 0B18H 0B19H 0B1AH 0B1BH 0B1CH 0B1DH 0B1EH0B1FH 0B20H 0B21H
Register T1/E1 Master Egress Serial Interface Mode Select T1/E1 Master Ingress Parity and Alarm Enable T1/E1 Master Egress Parity Enable T1/E1 Master Serial Interface Configuration T1/E1 Transmit Framing and Bypass Options T1/E1 Interrupt Source #1 T1/E1 Interrupt Source #2 T1/E1 Diagnostics T1/E1 PRBS Positioning and HDLC Control Reserved RJAT Interrupt Status RJAT Reference Clock Divisor N1 Control RJAT Output Clock Divisor N2 Control RJAT Configuration TJAT Interrupt Status TJAT Reference Clock Divisor N1 Control TJAT Output Clock Divisor N2 Control TJAT Configuration RX-ELST Configuration RX-ELST Interrupt Enable/Status RX-ELST Idle Code RX-ELST Reserved TX-ELST Configuration TX-ELST Interrupt Enable/Status TX-ELST Reserved RXCE Ingress Data Link Control RXCE Ingress Data Link Bit Select
PROPRIETARY AND CONFIDENTIAL
107
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0B22H0B27H 0B28H 0B29H 0B2AH0B2FH 0B30H 0B31H 0B32H 0B33H 0B34H 0B35H 0B36H 0B37H 0B38H 0B39H 0B3AH 0B3BH 0B3CH 0B3DH 0B3EH 0B3FH 0B40H 0B41H 0B42H 0B43H 0B44H 0B45H
Register RXCE Reserved TXCI Egress Data Link Control TXCI Egress Data Link Bit Select TXCI Reserved RPSC Configuration RPSC P Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer TPSC Configuration TPSC P Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer PMON Interrupt Enable/Status PMON Framing Bit Error Count PMON OOF/COFA/Far End Block Error Count (LSB) PMON OOF/COFA/Far End Block Error Count (MSB) PMON Bit Error/CRCE Count (LSB) PMON Bit Error/CRCE Count (MSB) PMON Reserved PMON Reserved RDLC Configuration RDLC Interrupt Control RDLC Status RDLC Data RDLC Primary Address Match RDLC Secondary Address Match
PROPRIETARY AND CONFIDENTIAL
108
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0B46H0B47H 0B48H 0B49H 0B4AH 0B4BH 0B4CH 0B4DH 0B4EH0B4FH 0B50H 0B51H 0B52H 0B53H 0B54H 0B55H 0B56H 0B57H 0B58H 0B59H 0B5AH 0B5BH 0B5CH 0B5DH 0B5EH 0B5FH 0B60H
Register Reserved TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Transmit Threshold TDPR Interrupt Enable TDPR Interrupt Status/UDR Clear TDPR Transmit Data Reserved PRBS Generator/Checker Control PRBS Checker Interrupt Enable/Status PRBS Pattern Select PRBS Reserved PRBS Error Count Register #1 PRBS Error Count Register #2 PRBS Error Count Register #3 PRBS Reserved SIGX Configuration/Change of Signaling State SIGX Channel Indirect Status/Change of Signaling State SIGX Channel Indirect Address/Control/ Change of Signaling State SIGX Channel Indirect Data Buffer/Change of Signaling State RX-SIG-ELST Configuration RX- SIG-ELST Interrupt Enable/Status RX- SIG-ELST Idle Code RX- SIG-ELST Reserved T1 ALMI Configuration
PROPRIETARY AND CONFIDENTIAL
109
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0B61H 0B62H 0B63H 0B64H 0B65H 0B66H 0B67H 0B68H 0B69H 0B6AH0B6BH 0B6CH 0B6DH 0B6EH 0B6FH 0B70H 0B71H 0B72H 0B73H 0B74H 0B75H 0B76H 0B77H 0B78H0B7FH 0B80H0BFFH 0C00H0C7FH
Register T1 ALMI Interrupt Enable T1 ALMI Interrupt Status T1 ALMI Alarm Detection Status T1 XBOC Control T1 XBOC Code T1 RBOC Enable T1 RBOC Code Status T1 XBAS Configuration T1 XBAS Alarm Transmit T1 XBAS Reserved T1 FRMR Configuration T1 FRMR Interrupt Enable T1 FRMR Interrupt Status T1 FRMR Reserved T1 APRM Configuration/Control T1 APRM Manual Load T1 APRM Interrupt Status T1 APRM One Second Content Octet 2 T1 APRM One Second Content Octet 3 T1 APRM One Second Content Octet 4 T1 APRM One Second Content MSB (Octet 5) T1 APRM One Second Content LSB (Octet 6) Reserved T1 Framer Slice #23 T1 Framer Slice #24
PROPRIETARY AND CONFIDENTIAL
110
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 0C80H0CFFH 0D00H0D7FH 0D80H0DFFH 0E00H0E7FH 0E80H0FFFH 1000H10FFH 1000H 1001H 1002H 1003H 1004H 1005H 1006H 1007H 1008H 1009H 100AH100BH 100CH 100DH 100EH 100FH 1010H 1011H
Register T1 Framer Slice #25 T1 Framer Slice #26 T1 Framer Slice #27 T1 Framer Slice #28 Reserved DS3 FRAMER and M13 Multiplexer DS3 Master Reset DS3 Master Data Source DS3 Master Unchannelized Interface Options DS3 Master Transmit Line Options DS3 Master Receive Line Options DS3 Master Alarm Enable DS2 Master Alarm Enable / DS3 Network Requirement Bit Reserved DS3 TRAN Configuration DS3 TRAN Diagnostic DS3 TRAN Reserved DS3 FRMR Configuration DS3 FRMR Interrupt Enable/Additional Configuration DS3 FRMR Interrupt Status DS3 FRMR Status DS3 PMON Performance Meters DS3 PMON Interrupt Enable/Status
PROPRIETARY AND CONFIDENTIAL
111
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 1012H 1013H 1014H 1015H 1016H 1017H 1018H 1019H 101AH 101BH 101CH 101DH 101EH 101FH 1020H 1021H 1022H 1023H 1024H 1025H 1026H1027H 1028H 1029H 102AH 102BH 102CH 102DH
Register DS3 PMON Reserved DS3 PMON Reserved DS3 PMON Line Code Violation Event Count LSB DS3 PMON Line Code Violation Event Count MSB DS3 PMON Framing Bit Error Event Count LSB DS3 PMON Framing Bit Error Event Count MSB DS3 PMON Excessive Zeros LSB DS3 PMON Excessive Zeros MSB DS3 PMON Parity Error Event Count LSB DS3 PMON Parity Error Event Count MSB DS3 PMON Path Parity Error Event Count LSB DS3 PMON Path Parity Error Event Count MSB DS3 PMON FEBE Event Count LSB DS3 PMON FEBE Event Count MSB DS3 TDPR Configuration DS3 TDPR Upper Transmit Threshold DS3 TDPR Lower Interrupt Threshold DS3 TDPR Interrupt Enable DS3 TDPR Interrupt Status/UDR Clear DS3 TDPR Transmit Data DS3 TDPR Reserved DS3 RDLC Configuration DS3 RDLC Interrupt Control DS3 RDLC Status DS3 RDLC Data DS3 RDLC Primary Address Match DS3 RDLC Secondary Address Match
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 102EH102FH 1030H 1031H 1032H 1033H 1034H 1035H1037H 1038H 1039H 103AH 103BH 103CH 103DH 103EH 103FH 1040H 1041H 1042H 1043H 1044H 1045H 1046H 1047H 1048H 1049H 104AH 104BH
Register DS3 RDLC Reserved PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD Tap PRGD Error Insertion PRGD Reserved PRGD Pattern Insertion Register #1 PRGD Pattern Insertion Register #2 PRGD Pattern Insertion Register #3 PRGD Pattern Insertion Register #4 PRGD Pattern Detector Register #1 PRGD Pattern Detector Register #2 PRGD Pattern Detector Register #3 PRGD Pattern Detector Register #4 MX23 Configuration MX23 Demux AIS Insert MX23 Mux AIS Insert MX23 Loopback Activate MX23 Loopback Request Insert MX23 Loopback Request Detect MX23 Loopback Request Interrupt MX23 Reserved FEAC XBOC Control FEAC XBOC Code FEAC RBOC Configuration/Interrupt Enable FEAC RBOC Interrupt Status
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 104CH105FH 1060H 1061H 1062H 1063H 1064H 1065H 1066H 1067H 1068H106FH 1070H 1071H 1072H 1073H 1074H 1075H1077H 1078H107FH 1080H1087H 1088H108FH 1090H1097H 1098H109FH 10A0H10A7H
Register Reserved DS2 FRMR #1 Configuration DS2 FRMR #1 Interrupt Enable DS2 FRMR #1 Interrupt Status DS2 FRMR #1 Status DS2 FRMR #1 Monitor Interrupt Enable/Status DS2 FRMR #1 FERR Count DS2 FRMR #1 PERR Count (LSB) DS2 FRMR #1 PERR Count (MSB) Reserved MX12 #1 Configuration and Control MX12 #1 Loopback Code Select MX12 #1 Mux/Demux AIS Insert MX12 #1 Loopback Activate MX12 #1 Loopback Interrupt MX12 #1 Reserved Reserved DS2 FRMR #2 Registers Reserved MX12 #2 Registers Reserved DS2 FRMR #3 Registers
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 10A8H10AFH 10B0H10B7H 10B8H10BFH 10C0H10C7H 10C8H10CFH 10D0H10D7H 10D8H10DFH 10E0H10E7H 10E8H10EFH 10F0H10F7H 10F8H10FFH 1100H1107H 1108H110FH 1110H1117H 1118H111FH 1120H1127H 1128H112FH
Register Reserved MX12 #3 Registers Reserved DS2 FRMR #4 Registers Reserved MX12 #4 Registers Reserved DS2 FRMR #5 Registers Reserved MX12 #5 Registers Reserved DS2 FRMR #6 Registers Reserved MX12 #6 Registers Reserved DS2 FRMR #7 Registers Reserved
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 1130H1137H 1138H16FFH 1700H179FH 1700H 1701H 1702H 1703H170FH 1710H 1711H 1712H 1713H 1714H 1715H 1716H 1717H 1718H171DH 171EH 171FH 1720H 1721H 1722H 1723H 1724H 1725H 1726H
Register MX12 #7 Registers Reserved SBI Interface SBI Master Reset / Bus Signal Monitor SBI Master Configuration SBI Bus Master Configuration SBI Reserved EXSBI Control EXSBI FIFO Underrun Interrupt Status EXSBI FIFO Overrun Interrupt Status EXSBI Tributary RAM Indirect Access Address EXSBI Tributary RAM Indirect Access Control EXSBI Reserved EXSBI Tributary Control Indirect Access Data EXSBI SBI Parity Error Interrupt Status EXSBI Reserved EXSBI Depth Check Interrupt Status EXSBI Extract External ReSynch Interrupt Status INSBI Control INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Tributary Register Indirect Access Address INSBI Tributary Register Indirect Access Control INSBI Reserved INSBI Tributary Control Indirect Access Data
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Address 1727H172FH 1731H 1732H 1733H173FH 1740H175FH 1780H179FH 1780H1FFFH
Register INSBI Reserved INSBI Depth Check Interrupt Status INSBI Insert External ReSynch Interrupt Status INSBI Reserved SBI SIPO Reserved SBI PISO Reserved Reserved
For all register accesses, CSB must be low.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the TECT3. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[13]) is low. Notes on Normal Mode Register Bits: 1) Writing values into unused register bits typically has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bit must be written with logic 0. Reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2) All configuration bits that can be written into can also be read back. This allows the processor controlling the TECT3 to determine the programming state of the block. 3) Writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4) Writing into read-only normal mode register bit locations does not affect TECT3 operation unless otherwise noted. The register descriptions are contained in a separate TECT3 register description document.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
11
TEST FEATURES DESCRIPTION The TECT3 contains test features for both production testing and board testing. Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the TECT3. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[13]) is high. Notes on Register Bits: 1) Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. Writeable register bits are not initialized upon reset unless otherwise noted.
2)
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Register 2000H: Master Test Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W R/W W R/W Type Function Unused Unused Unused PMCTST DBCTRL IOTST HIZDATA HIZIO Default X X X X X X X X
This register is used to select TECT3 test features. All bits, except for PMCTST, are reset to zero by a hardware reset of the TECT3; a software reset of the TECT3 does not affect the state of the bits in this register. PMCTST: The PMCTST bit is used to configure the TECT3 for PMC's manufacturing tests. When PMCTST is set to logic 1, the TECT3 microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can only be cleared by setting CSB to logic 1. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin while IOTST is a logic 1. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the TECT3 to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. When IOTST and PMCTST are both logic 0, the DBCTRL bit is ignored. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the TECT3 for board level testing. When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate
PROPRIETARY AND CONFIDENTIAL
120
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
the outputs of the block and consequently the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). HIZIO: The HIZIO bit controls the tri-state modes of the output pins of the TECT3. While the HIZIO bit is a logic 1, all output pins of the TECT3, except the data bus, are held in a high-impedance state. The microprocessor interface is still active. HIZDATA: The HIZDATA bit controls the tri-state modes of the TECT3. While the HIZIO bit is a logic 1, all output pins of the TECT3, except the data bus, are held in a high-impedance state. While the HIZDATA bit is a logic 1, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. 11.1 JTAG Test Port The TECT3 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Table 3: Instruction Register Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Code IR[2:0] 000 001 010 011 100 101 110 111
PROPRIETARY AND CONFIDENTIAL
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 4: Identification Register Length Version number Part Number Manufacturer's identification code Device identification 11.1.1 Boundary Scan Register The boundary scan register is made up of 286 boundary scan cells, divided into inout observation (IN_CELL), output (OUT_CELL) and bidirectional (IO_CELL) cells. These cells are detailed in the following pages. The first 32 cells form the ID code register and carry the code 383150CDH. The cells are arranged as follows: Table 5: Boundary Scan Chain Pin/Enable HIZ ICLK[28] ICLK[27] ICLK[20] ICLK[19] IFP[19] ECLK[28]_OEN ECLK[28] ECLK[27]_OEN ECLK[27] ECLK[20]_OEN ECLK[20] ECLK[19]_OEN ECLK[19] ECLK[12]_OEN Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cell Type OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL Device I.D. 32 bits 3H 8315 0CDH 383150CDH
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable ECLK[12] ECLK[11]_OEN ECLK[11] IFP[12] IFP[11] ICLK[12] ICLK[11] ID[12] ID[11] ID[26]_CASID[7] ID[25]_MVID[7] ICLK[26] ICLK[25] IFP[26] IFP[25] ECLK[26]_OEN ECLK[26] ECLK[25]_OEN ECLK[25] ED[26]_CASED[7] ED[25]_MVED[7] ED[18]_CASED[5] CTCLK CECLK_CMV8MCLK CEFP_CMVFPB CICLK_CMVFPC CIFP CCSED
Register Bit 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Cell Type IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable ED[17]_MVED[5] CLK52M ED[10]_CASED[3] CCSID ECLK[18]_OEN ECLK[18] ECLK[17]_OEN ECLK[17] ECLK[10]_OEN ECLK[10] ED[9]_MVED[3] ICLK[18] ICLK[17] ID[18]_CASID[5] ID[17]_MVID[5] IFP[18] IFP[17] IFP[10] IFP[9] IFP[2] ID[10]_CASID[3] ID[9]_MVID[3] ICLK[10] ICLK[9] ECLK[9]_OEN ECLK[9] ECLK[2]_OEN ECLK[2]
Register Bit 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Cell Type IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable ICLK[2] ED[2]_CASED[1]_TFPI_TMFPI ECLK[1]_TGAPCLK_OEN ECLK[1]_TGAPCLK ED[1]_MVED[1]_TDATI ID[1]_MVID[1]_RDATO ID[2]_CASID[1]_ROVRHD ICLK[1]_RSCLK IFP[1]_RFPO_RMFPO TICLK RCLK RPOS_RDAT RNEG_RLCV TCLK TPOS_TDAT TNEG_TMFP UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED
Register Bit 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
Cell Type OUT_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED UNCONNECTED LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0
Register Bit 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
Cell Type OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
Device I.D. -
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable LOGIC 0 LOGIC 0 LOGIC 0 LOGIC 0 ICLK[3] ICLK[4] ID[3] ECLK[3]_OEN ECLK[3] ECLK[4]_OEN ECLK[4] ECLK[5]_OEN ECLK[5] IFP[3] IFP[4] IFP[5] IFP[6] IFP[13] IFP[14] ICLK[5] ICLK[6] ECLK[6]_OEN ECLK[6] ECLK[13]_OEN ECLK[13] ECLK[14]_OEN ECLK[14] ECLK[21]_OEN
Register Bit 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154
Cell Type IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
Device I.D. -
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127
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable ECLK[21] ECLK[22]_OEN ECLK[22] ECLK[7]_OEN ECLK[7] ECLK[8]_OEN ECLK[8] IFP[21] IFP[22] ID[4] ID[5]_MVID[2] ID[6]_CASID[2] ID[13]_MVID[4] ID[14]_CASID[4] ED[3] ED[4] ED[5]_MVED[2] ED[6]_CASED[2] ED[13]_MVED[4] ED[14]_CASED[4] ID[21]_MVID[6] ID[22]_CASID[6] ICLK[13] ICLK[14] IFP[7] IFP[8] IFP[15] IFP[16]
Register Bit 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182
Cell Type IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable IFP[23] IFP[24] ICLK[21] ICLK[22] ICLK[7] ICLK[8] ID[7] ID[8] ICLK[15] ICLK[16] ICLK[23] ICLK[24] ED[22]_CASED[6] ED[21]_MVED[6] RECVCLK1 RECVCLK2 XCLK ECLK[15]_OEN ECLK[15] ECLK[16]_OEN ECLK[16] ECLK[23]_OEN ECLK[23] ECLK[24]_OEN ECLK[24] RSTB A[13] A[12]
Register Bit 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Cell Type OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RDB WRB ALE INTB CSB D[0]_OEN D[0] D[1]_OEN D[1] D[2]_OEN D[2] D[3]_OEN D[3] D[4]_OEN D[4] D[5]_OEN
Register Bit 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238
Cell Type IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
Device I.D. -
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable D[5] D[6]_OEN D[6] D[7]_OEN D[7] ID[15]_SDDATA[0]_OEN ID[15]_SDDATA[0] ID[16]_SDDATA[1]_OEN ID[16]_SDDATA[1] ID[19]_SDDATA[2]_OEN ID[19]_SDDATA[2] ID[20]_SDDATA[3]_OEN ID[20]_SDDATA[3] ID[23]_SDDATA[4]_OEN ID[23]_SDDATA[4] ID[24]_SDDATA[5]_OEN ID[24]_SDDATA[5] ID[27]_SDDATA[6]_OEN ID[27]_SDDATA[6] ID[28]_SDDATA[7]_OEN ID[28]_SDDATA[7] IFP[20]_SDDP_OEN IFP[20]_SDDP IFP[28]_SDV5_OEN IFP[28]_SDV5 IFP[27]_SDPL_OEN IFP[27]_SDPL SAJUST_REQ_OEN
Register Bit 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266
Cell Type IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
Device I.D. 1 0 1 1 0 0 1 1 0 0 0 0 1
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Pin/Enable SAJUST_REQ SBIACT_OEB SBIACT SBIDET[0] ED[7]_SBIDET[1] SREFCLK SC1FP_OEN SC1FP ED[15]_SADATA[0] ED[16]_SADATA[1] ED[19]_SADATA[2] ED[20]_SADATA[3] ED[23]_SADATA[4] ED[24]_SADATA[5] ED[27]_SADATA[6] ED[28]_SADATA[7] ED[8]_SADP ED[12]_SAPL ED[11]_SAV5 TDO TDI TCK TMS TRSTB Notes:
Register Bit 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285
Cell Type OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL TAP Output TAP Input TAP Clock TAP Input TAP Input
Device I.D. 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 -
1. Register bit 285 is the first bit of the scan chain (closest to TDI). 2. Enable cell pinname_OEN, tristates pin pinname when set high.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
3. Enable cell HIZ, tristates all pins that do not have an individual pinname_OEN enable signal.
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
12
OPERATION
12.1 DS3 Frame Format The TECT3 provides support for both the C-bit parity and M23 DS3 framing formats. The DS3 frame format is shown in Figure 27. Figure 27: DS3 Frame Structure
84 bits M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 M-subframe 4 P 2 M-subframe 5 M1 M-subframe 6 M2 M-subframe 7 M3 F1 F1 F1 F1 F1 F1 F1 84 bits C1 C1 C1 C1 C1 C1 C1 84 bits F2 F2 F2 F2 F2 F2 F2 84 bits C2 C2 C2 C2 C2 C2 C2 84 bits F3 F3 F3 F3 F3 F3 F3 84 bits C3 C3 C3 C3 C3 C3 C3 84 bits F4 F4 F4 F4 F4 F4 F4 84 bits
Xx: X-Bit Channel * Transmit: The TECT3 inserts the FERF signal on the X-bits. FERF generation is controlled by either the FERF bit of the DS3 TRAN Configuration register or by detection of OOF, RED, LOS and AIS, as configured by the TECT3 Master DS3 Alarm Enable register. Receive: The TECT3 monitors the state and detects changes in the state of the FERF signal on the X-bits.
*
Px: P-Bit Channel * * Transmit: The TECT3 calculates the parity for the payload data over the previous M-frame and inserts it into the P1 and P2 bit positions. Receive: The TECT3 calculates the parity for the received payload. Errors are accumulated in the DS3 PMON Parity Error Event Count registers.
Mx: M-Frame Alignment Signal * * Transmit: The TECT3 generates the M-frame alignment signal (M1 = 0, M2 = 1, M3 = 0). Receive: The TECT3 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. M-bit errors are counted in the DS3 PMON Framing Bit Error Event Count
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
registers. When one or more M-bit errors are detected in 3 out of 4 consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the DS3 Framer Configuration register is a logic 0). Fx: M-Subframe Alignment Signal * * Transmit: The TECT3 generates the M-Subframe Alignment signal (F1=1, F2=0, F3=0, F4=1). Receive: The TECT3 finds M-frame alignment by searching for the F-bits and the M-bits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. F-bit errors are counted in the DS3 PMON Framing Bit Error Event Count registers. An out-of frame defect is asserted if 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration register).
Cx: C-Bit Channels * Transmit: When configured for M23 applications, the C-bits are forced to logic 1 with the exception of the C-bit Parity ID bit (the first C-bit of the first M-subframe), which is forced to toggle every M-frame. When configured for C-bit parity applications, the C-bit Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The third C-bit in M-subframe 1 provides a far-end alarm and control (FEAC) signal. The FEAC channel is sourced by the DS3 XBOC block. The 3 Cbits in M-subframe 3 carry path parity information. The value of these 3 Cbits is the same as that of the P-bits. The 3 C-bits in M-subframe 4 are the FEBE bits. FEBE transmission is controlled by the DFEBE bit in the DS3 TRAN Diagnostic register and by the detection of receive framing bit and path parity errors. The 3 C-bits in M-subframe 5 contain the 28.2 kbit/s path maintenance datalink. These bits are inserted from the DS3 TDPR HDLC controller. The C-bits in M-subframes 2, 6, and 7 are unused and are set to logic 1. Receive: The CBITV register bit in the DS3 FRMR Status register is used to report the state of the C-bit parity ID bit, and hence whether a M23 or Cbit parity DS3 signal stream is being received. The FEAC channel on the third C-bit in M-subframe 1 is detected by the DS3 RBOC block. Path parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are reported in the DS3 PMON Path Parity Error Event Count and FEBE Event Count registers respectively. The path maintenance datalink signal is extracted by theDS3 RDLC HDLC receiver (if enabled).
*
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
12.2 Servicing Interrupts The TECT3 will assert INTB to logic 0 when a condition which is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. Read the bits of the TECT3 Master Interrupt Source register (0020H) to identify which of the eight interrupt registers (0021H-0028H) needs to be read to identify the interrupt. For example, a logic one read in the DS3INT register bit indicates that an interrupt identified in the Master Interrupt Source DS3 register produced the interrupt. 2. Read the bits of the second level Master Interrupt Source register to identify the interrupt source. 3. Service the interrupt. 4. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB 12.3 Using the Performance Monitoring Features The PMON blocks are provided for performance monitoring purposes. The DS3 PMON block is used to monitor DS3 performance primitives. The PMON blocks within each T1/E1 Framer slice are used to monitor T1 or E1 performance primitives. The counters in the DS3 PMON block has been sized as not to saturate if polled every second. The T1/E1 PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%). An accumulation interval is initiated by writing to one of the PMON event counter register addresses or by writing to the Master Revision/Global PMON Update register. After initiating an accumulation interval, 3.5 recovered clock periods (RCLK for the DS3 PMON) must be allowed to elapse to permit the PMON counter values to be properly transferred before the PMON registers may be read. The odds of any one of the T1/E1 counters saturating during a one second sampling interval go up as the bit error rate (BER) increases. At some point, the probability of counter saturation reaches 50%. This point varies, depending upon the framing format and the type of event being counted. The BER at which the probability of counter saturation reaches 50% is shown for various counters in Table 6 for E1 mode, and in Table 7 for T1 mode.
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Table 6: PMON Counter Saturation Limits (E1 mode) Counter FER CRCE FEBE BER 4.0 X 10-3 cannot saturate cannot saturate
Table 7: PMON Counter Saturation Limits (T1 mode) Counter FER CRCE Format SF ESF SF ESF BER 1.6 x 10-3 6.4 x 10-2 1.28 x 10-1 cannot saturate
Below these 50% points, the relationship between the BER and the counter event count (averaged over many one second samples) is essentially linear. Above the 50% point, the relationship between BER and the average counter event count is highly non-linear due to the likelihood of counter saturation. The following figures show this relationship for various counters and framing formats. These graphs can be used to determine the BER, given the average event count. In general, if the BER is above 10-3, the average counter event count cannot be used to determine the BER without considering the statistical effect of occasional counter saturation. Figure 28 illustrates the expected count values for a range of Bit Error Ratios in E1 mode.
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Figure 28: FER Count vs. BER (E1 mode)
9 Bit Error Rate (x 10 -3 ) 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 Framing Bit Error Count Per Second Average Count Over Many 1 Second Intervals
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-4 error is often due to more than one bit error. Thus, the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same explanation holds for the FEBE event counter. The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the following equation:
ae 8 ae oo c log c 1CRCE / / c e 8000 o/ c / 8*256 c / c / e o
Bit Error Rate = 1 - 10
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Figure 29: CRCE Count vs. BER (E1 mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 200 400 600 CRCE 800 1000 1200
Figure 30 illustrates the expected count values for a range of Bit Error Ratios in T1 mode. Figure 30: FER Count vs. BER (T1 ESF mode)
9
2 -
)
8 7 6 5 4 3 2 1 0 0
Average Count Over Many 1 Second Intervals
0 1 x ( e t a R r o r r E t i B
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At BERs below 10-4, there tends to be no more than one bit error per superframe, so the number of CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus, the relationship between BER and BEE count becomes nonlinear above a 10-4 BER. This must be taken into account when using ESF CRC-6 counts to determine the BER.
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The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the following equation:
ae 24 ae oo c log c 1BEE / / c e 8000 o/ / c 24*193 / c / c o e
Bit Error Rate = 1 - 10
Figure 31: CRCE Count vs. BER (T1 ESF mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 50 100 150 200 250 300 350 CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and should be ignored. Figure 32: CRCE Count vs. BER (T1 SF mode)
20
2 -
)
18 16 14 12 10 8 6 4 2 0 0 200 400
Average Count Over Many 1 Second Intervals
0 1 x ( e t a R r o r r E t i B
600
800
1000
1200
Bit Error Event Count Per Second
12.4 Using the Internal FDL Transmitter It is important to note that access rate to the TDPR registers is limited by the rate of the internal high-speed system clock which is either the DS3, DS1 or E1 clock. Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR
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Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 1/8 that of the selected TDPR high-speed system clock. This time is used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the TDPR registers. Upon reset of the TECT3, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones Idle signal will be sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the one of the TECT3 Master Interrupt Source registers, and the TECT3 TDPR Interrupt Status registers to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register. Interrupt Driven Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The
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TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for a complete packet to be transmitted. Once data is available to be transmitted, then go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes of the packet have been written to the Transmit Data register, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Unless an error condition occurs, transmission will not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns. TDPR Interrupt Routine: Upon assertion of INTB, the source of the interrupt must first be identified by reading the TECT3 Master Interrupt Source register (0020H) followed by reading one of the second level master interrupt source registers T1E1INT1, T1E1INT2, T1E1INT3, T1E1INT4 or DS3INT. Once the source of the interrupt has been identified as the TDPR in use, then the following procedure should be carried out: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value.
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3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data. 5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted. If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level. Polling Mode: The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets:
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1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6. 5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, then go to step 2. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 12.5 Using the Internal Data Link Receiver It is important to note that the access rate to the RDLC registers is limited by the rate of the internal high-speed system clock which is either the DS3, DS1 or E1 system clock. Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed at a rate no faster than 1/10 that of the selected RDLC high-speed system clock. This time is used by the high-speed system clock to sample the event and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read RDLC registers. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit. After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the
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FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC uses the TECT3 INTB output and the TECT3 Master Interrupt Source registers to determine when to read the RDLC Data register. In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the TECT3 is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the TECT3 Master Interrupt Source register followed by one of the second level master interrupt source registers to identify one of the 29 HDLC receivers as the interrupt source. Once it has identified that the RDLC has generated the interrupt, it processes the data in the following order: 1. Read the RDLC Status register. The INTR bit should be logic 1. 2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 3. If COLS = 1, then set the EMPTY FIFO software flag. 4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO
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software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 5. Read the RDLC Data register. 6. Read the RDLC Status register. 7. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 8. If COLS = 1, then set the EMPTY FIFO software flag. 9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag. If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. If PBS[2:0] = 000, store the packet data. 11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt. The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
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Figure 33: Typical Data Frame BIT: 8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
FLAG
Address (high) (low)
CONTROL
data bytes received and transferred to the FIFO Buffer
Frame Check Sequence 0 1 1 1 1 1 1 0
FLAG
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. Figure 34: Example Multi-Packet Operational Sequence
DATA INT FE LA FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 1 2 3 45 6 7
F A D INT FE LA
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
Figure 34 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and
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the processing required at each point is described in the following paragraphs. The actual interrupt signal, INTB, is active low and will be the inverse of the INT signal shown in Figure 16. Also in this example, the programmable fill level set point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC Interrupt Control register. At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes active. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1. At points 2 and 6 the last byte of a packet is detected and interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO. At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared. 12.6 T1 Automatic Performance Report Format Table 8: Performance Report Message Structure and contents Octet No. 1 2 3 4 5 6 7 8 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FLAG SAPI C/R EA TEI EA CONTROL G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI G3 LV G4 U1 U2 G5 SL G6 FE SE LB G1 R G2 Nm NI
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9 10 11 12 13 14 15 Notes:
G3 FE G3 FE
LV SE LV SE
G4 LB G4 LB
U1 U2 G1 R U1 U2 G1 R FCS FCS FLAG
G5 G2 G5 G2
SL Nm SL Nm
G6 NI G6 NI
1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8). Table 9: Performance Report Message Structure Notes Octet No. 1 2 3 4 5,6 7,8 9,10 11,12 13,14 15 Octet Contents 01111110 00111000 00111010 00000001 00000011 Variable Variable Variable Variable Variable 01111110 Interpretation Opening LAPD Flag From CI: TEI=0,EA=1 Unacknowledged Frame Data for latest second (T') Data for Previous Second(T'-1) Data for earlier Second(T'-2) Data for earlier Second(T'-3) CRC16 Frame Check Sequence Closing LAPD flag SAPI=14, C/R=0, EA=0 From carrier: SAPI=14,C/R=1,EA=0
Table 10: Performance Report Message Contents Bit Value G1=1 G2=1 G3=1 Interpretation CRC ERROR EVENT =1 1PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
G4=1 G5=1 G6=1 SE=1 FE=1 LV=1 SL=1 LB=1 U1,U2=0 R=0 NmNI=00,01,10,11
1012.7 Using the Per-Channel Serial Controllers 12.7.1 Initialization Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. The output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 1. 12.7.2 Direct Access Mode Direct access mode to the TPSC or RPSC is not used in the TECT3. However, direct access mode is selected by default whenever the TECT3 is reset. The IND bit within the TPSC and RPSC Configuration Registers must be set to logic 1 after a reset is applied. 12.7.3 Indirect Access Mode Indirect access mode is selected by setting the IND bit in the TPSC or RPSC Configuration Register to logic 1. When using the indirect access mode, the status of the BUSY indication bit should be polled to determine the status of the
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microprocessor access: when the BUSY bit is logic 1, the TPSC or RPSC is processing an access request; when the BUSY bit is logic 0, the TPSC or RPSC has completed the request. The indirect write programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write the channel data to the TPSC (RPSC) Channel Indirect Data Buffer register. 3. Write RWB=0 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step 3 and remain at logic 1 until the request is complete. 5. If there is more data to be written, go back to step 1. The indirect read programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write RWB=1 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately after step 2 and remain at logic 1 until the request is complete. 4. Read the requested channel data from the TPSC (RPSC) Channel Indirect Data Buffer register. 5. If there is more data to be read, go back to step 1. 12.8 T1/E1 Framer Loopback Modes The TECT3 provides three loopback modes for T1/E1 links to aid in network and system diagnostics. The internal T1/E1 line loopback can be initiated at any time via the P interface, but is usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through
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the framer. The payload can also be looped-back on a per-DS0 basis to allow network testing without taking an entire DS1 off-line. T1/E1 Line Loopback T1/E1 Line loopback is initiated by setting the LLOOP bit to a 1 in the T1/E1 Diagnostics register (000DH + N*80H, N=1 to 28). When in line loopback mode the appropriate T1/E1 framer in the TECT3 is configured to internally connect the jitter-attenuated clock and data from the RJAT to the transmit clock and data (shown as TxD[x] and TxCLK[x] in the lineloopback diagram) going to the M13 mux. The RJAT may be bypassed if desired. Conceptually, the data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 35. Figure 35: T1/E1 Line Loopback
CTCLK*
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I ti Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TxCLK[1:28] TxD[1:28]
ED[1:28] ECLK[1:28]/EFP[1:28]/ ESIG[1:28] CEFP* CECLK*
ESIF Egress Interface
CICLK* CIFP* ID[1:28] ICLK[1:28]/ISIG[1:28] IFP[1:28]
ELST Elastic Store ISIF Ingress Interface
FRAM Framer/ Slip Buffer RAM T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction
Li ne L oopback
RxCLK[1:28] RxD[1:28]
RJAT Digital Jitter Attenuator
RECEIVER
T1/E1 Diagnostic Digital Loopback When Diagnostic Digital loopback is initiated, by writing a 1 to the DLOOP bit in the T1/E1 Diagnostics register (000DH + N*80H, N=1 to 28), the appropriate T1/E1 framer in the TECT3 is configured to internally connect its transmit clock and data (shown as TxD[x] and TxCLK[x] in the diagnostic loopback figure) to the
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
receive clock and data (shown as RxD[x] and RxCLK[x] in the diagnostic loopback figure) The data flow through a single T1/E1 framer in this loopback condition is illustrated in Figure 36. Figure 36: T1/E1 Diagnostic Digital Loopback
CTCLK*
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I ti Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TxCLK[1:28] TxD[1:28]
ED[1:28] ECLK[1:28]/EFP[1:28]/ ESIG[1:28] CEFP* CECLK*
ESIF Egress Interface
Di agn ost i c Loopb ack
CICLK* CIFP* ID[1:28] ICLK[1:28]/ISIG[1:28] IFP[1:28] FRAM Framer/ Slip Buffer RAM T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator RxCLK[1:28] RxD[1:28]
ELST Elastic Store ISIF Ingress Interface
RECEIVER
Per-Channel Loopback The T1/E1 payload may be looped-back on a per-channel basis through the use of the TPSC. If all channels are looped-back, the result is very similar to Payload Loopback on other PMC framers. In order for per-channel loopback to operate correctly, the Ingress Interface must be in Clock Master mode. The LOOP bit must be set to logic 1 in the TPSC Internal Registers for each channel desired to be looped back, and the PCCE bit must be set to logic 1 in the TPSC Configuration register. When all these configurations have been made, the ingress DS0s or timeslots selected will overwrite their corresponding egress channels; the remaining egress channels will pass through intact. Note that because the egress and ingress streams will not be superframe aligned, that any robbed-bit signaling in the ingress stream may not fall in the correct frame once looped-back, and that egress robbed-bit signaling will overwrite the looped-back channel data if signaling insertion is enabled. PRBS generation and detection is
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
not available in payload loopback mode. The data flow in per-channel loopback is illustrated in Figure 37. Figure 37: Per-Channel Loopback
CTCLK*
TRANSMITTER
T1-XBAS/E1-TRAN BasicTransmitter: Frame Generation, Alarm Insertion, Signaling Trunk Conditioning I ti Line Coding TOPS Timing Options TJAT Digital Jitter Attenuator TxCLK[1:28] TxD[1:28]
ED[1:28] ECLK[1:28]/EFP[1:28]/ ESIG[1:28] CEFP* CECLK*
ESIF Egress Interface TPSC Per-DS0 Serial Controller
MUX
Per - DS0 Loopback
FRAM Framer/ Slip Buffer RAM T1/E1-FRMR Framer: Frame Alignment, Alarm Extraction RJAT Digital Jitter Attenuator RxCLK[1:28] RxD[1:28]
ID[1:28] ICLK[1:28]/ISIG[1:28] IFP[1:28]
ELST Elastic Store ISIF Ingress Interface
RECEIVER
12.9 DS3 Loopback Modes The TECT3 provides three DS3 M13 multiplexer loopback modes to aid in network and system diagnostics at the DS3 interface. The DS3 loopbacks can be initiated via the P interface whenever the DS3 framer/M13 multiplexer is enabled. The DS3 Master Data Source register controls the DS3 loopback modes. DS3 Diagnostic Loopback DS3 Diagnostic Loopback allows the transmitted DS3 stream to be looped back into the receive DS3 path, overriding the DS3 stream received on the RDAT/RPOS and RNEG/RLCV inputs. The RCLK signal is also substituted with the transmit DS3 clock, TCLK. While this mode is active, AIS may be substituted for the DS3 payload being transmitted on the TPOS/TDAT and TNEG/TMFP outputs. The configuration of the receive interface determines how the TNEG/TMFP signal is handled during loopback: if the UNI bit in the DS3 FRMR register is set, then the receive interface is configured for RDAT and RLCV,
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
therefore the TNEG/TMFP signal is suppressed during loopback so that transmit MFP indications will not be seen nor accumulated as input LCVs. If the UNI bit is clear, then the interface is configured for bipolar signals RPOS and RNEG, therefore the TNEG is fed directly to the RNEG input. This diagnostic loopback can be used when configured as a multiplexer or as a framer only. The DS3 loopback mode is shown diagrammatically in Figure 38. Figure 38: DS3 Diagnostic Loopback Diagram
RCLK RPOS/ RDAT RNEG/ RLCV
DS3 FRMR
MX23
UNI TCLK TPOS/ TDAT TNEG/ TMFP Optional AIS Insertion
DS3 TRAN
F MX12 #7 R F MX12 #6 M R FR MX12 #5 M R FR MX12 #4 M R F MR MX12 #3 RR F MX12 #2 M F RR MX12 #1 RM MR R
DS3 Line Loopback DS3 Line Loopbacks allow the received DS3 streams to be looped back into the transmit DS3 paths, overriding the DS3 streams created internally by the multiplexing of the lower speed tributaries. The transmit signals on TPOS/TDAT and TNEG/TMFP are substituted with the receive signals on RPOS/RDAT and RNEG/RLCV. The TCLK signal is also substituted with the receive DS3 clock, RCLK. While this mode is active, AIS may be substituted for the DS3 payload being transmitted on the TPOS/TDAT and TNEG/TMFP outputs. Note that the transmit interface must be configured to be the same as the DS3 FRMR receive interface for this mode to work properly. The DS3 line loopback mode is shown diagrammatically in Figure 39. There is a second form of line loopback which only loops back the DS3 payload. In this mode the DS3 framing overhead is regenerated for the received DS3 stream and then retransmitted. Line loopback is selected with the LLOOP bit in the DS3 Master Data source register and payload loopback is selected by the PLOOP bit in the same register.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 39: DS3 Line Loopback Diagram
RCLK RPOS/ RDAT RNEG/ RLCV
DS3 FRMR
MX23
TCLK TPOS/ TDAT TNEG/ TMFP
DS3 TRAN
F MX12 #7 R F MX12 #6 M R FR MX12 #5 M R FR MX12 #4 M RR F M MX12 #3 R FR MX12 #2 M R MX12 #1 FR RM MR R
DS2 Demultiplex Loopback DS2 Demultiplex Loopbacks allow each of the seven demultiplexed DS2 streams to be looped back into the MX23 and multiplexed up into the transmit DS3 stream. This overrides the tributary DS2 streams coming from the MX12s. The DS2 loopback mode is shown diagrammatically in Figure 40 and is enabled via the MX23 Loopback Activate register. Figure 40: DS2 Loopback Diagram
RCLK RPOS/ RDAT RNEG/ RLCV
DS3 FRMR MX23
Optional DEMUX AIS Insertion
DS2 Tributary Loopback path TCLK TPOS/ TDAT TNEG/ TMFP
DS3 TRAN
F MX12 #7 F R MX12 #6 RM FR MX12 #5 M R F MR MX12 #4 RR F M MX12 #3 R F MR MX12 #2 F RR MX12 #1 M R MR R
.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
12.10 SBI Bus Data Formats The TECT3 uses the Scaleable Bandwidth Interconnect (SBI) bus as a high density link interconnect with devices processing T1s and DS3s. The SBI bus is a multi-point to multi-point bus capable of interconnecting up to three TECT3 devices in parallel with other link layer or tributary processing devices. Multiplexing Structure The SBI structure uses a locked SONET/SDH structure fixing the position of the TU-3 relative to the STS-3/STM-1. The SBI is also of fixed frequency and alignment as determined by the reference clock (SREFCLK) and frame indicator signal (SC1FP). Frequency deviations are compensated by adjusting the location of the T1/DS3 channels using floating tributaries as determined by the V5 indicator and payload signals (SDV5, SAV5, SDPL and SAPL). Table 11 shows the bus structure for carrying T1 and DS3 tributaries in a SDH STM-1 like format. Up to 84 T1s or 3 DS3s are carried within the octets labeled SPE1, SPE2 and SPE3 in columns 16-270. All other octets are unused and are of fixed position. The frame signal (SC1FP) occurs during the octet labeled C1 in Row 1 column 7. The multiplexed links are separated into three Synchronous Payload Envelopes called SPE1, SPE2 and SPE3. Each envelope carries up to 28 T1s or a DS3. SPE1 carries the T1s numbered 1,1 through 1,28 or DS3 number 1,1. SPE2 carries T1s numbered 2,1 through 2,28 or DS3 number 2,1. SPE3 carries T1s numbered 3,1 through 3,28 or DS3 number 3,1. The most significant bit in all formats is the first bit of transmission.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 11: Structure for Carrying Multiplexed Links
SBI Column 1 Row 1 2 6 7 8 15 16 17 18 19 268 269 270
- *** - C1 - *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2SPE3 - *** - *** - SPE1SPE2SPE3SPE1 *** SPE1SPE2SPE3
9
1
2
3
3
- SPE1SPE2SPE3SPE1 5 6 6 6 7
SPE1SPE2SPE3 90 90 90
SPE Column
The TECT3, when enabled for SBI interconnection, will add and drop either 28 T1s or a DS3 into one of the three Synchronous Payload Envelopes, SPE1, SPE2 or SPE3. Tributary Numbering Tributary numbering for T1 uses the SPE number, followed by the Tributary number within that SPE and are numbered sequentially. Table 12 shows the T1 column numbering and relates the tributary number to the SPE column numbers and overall SBI column structure. Numbering for DS3 follows the same naming convention even though there is only one DS3 per SPE. SBI columns 16-18 are unused for T1 tributaries. Table 12: T1 Tributary Column Numbering T1#
1,1 2,1 3,1 1,2 2,2
***
SPE1 Column SPE2 Column SPE3 Column
7,35,63 7,35,63 7,35,63 8,36,64 8,36,64 34,62,90 34,62,90 34,62,90
SBI Column
19,103,187 20,104,188 21,105,189 22,106,190 23,107,191 100,184,268 101,185,269 102,186,270
1,28 2,28 3,28
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
SBI Timing Master Modes The TECT3 supports both synchronous and asynchronous SBI timing modes. Synchronous modes apply only to T1 tributaries and are used with ingress elastic stores to rate adapt the receive tributaries to the fixed SBI data rate. Asynchronous modes allow T1 and DS3 to float within the SBI structure to accommodate differences in timing. Note that Synchronous mode SBI timing operation is required for support of Channel Associated Signaling (CAS). In synchronous SBI mode the T1 DS0s are in a fixed format and do not move relative to the SBI structure. The SBI frame pulse, SC1FP, in synchronous mode can be enabled to indicate CAS signaling multi-frame alignment by pulsing once every 12th 2KHz SC1FP frame pulse period. SREFCLK sets the ingress rate from the receive elastic store. In Asynchronous modes timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures within the SBI. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet be passing an extra octet in the V3 octet locations (H3 octet for DS3 mappings). When the source is slower than the SBI bus, the floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI control signals. On the DROP BUS the TECT3 is timing master as determined by the arrival rate of data over the SBI. On the ADD BUS the TECT3 can be either the timing master or the timing slave. When the TECT3 is the timing slave it receives its transmit timing information from the arrival rate of data across the SBI ADD bus. When the TECT3 is the timing master it signals devices on the SBI ADD bus to speed up or slow down with the justification request signal, SAJUST_REQ. The TECT3 as timing master indicates a speedup request to a Link Layer SBI device by asserting the justification request signal high during the V3 or H3 octet. When this is detected by the Link Layer it will speed up the channel by inserting extra data in the next V3 or H3 octet. The TECT3 indicates a slowdown request to the Link Layer by asserting the justification request signal high during the octet after the V3 or H3 octet. When detected by the Link Layer it will retard the channel by leaving the octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request.
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
SBI Link Rate Information The TECT3 SBI bus provides a method for carrying link rate information between devices. This is optional on a per channel basis. Two methods are specified, one for T1 channels and the second for DS3 channels. These methods use the reference 19.44MHz SBI clock and the SC1FP frame synchronization signal to measure channel clock ticks and clock phase for transport across the bus. The T1 method allows for a count of the number of T1 rising clock edges between 2 KHz SC1FP frame pulses. This count is encoded in ClkRate[1:0] to indicate that the nominal number of clocks, one more than nominal or one less than nominal should be generated during the SC1FP period. This method also counts the number of 19.44MHz clock rising edges after sampling SC1FP high to the next rising edge of the T1 clock, giving the ability to control the phase of the generated clock. The link rate information passed across the SBI bus via the V4 octet and is shown in Table 13. Table 14 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet. Table 13: SBI T1 Link Rate Information SC1FP SREFCLK T1/E1 CLK Link Rate Octet T1/E1 Format Bit # 7 ALM *** *** ***
Clock Count
a 5:4
Phase 3:0 Phase[3:0]
a
6 0
ClkRate[1:0]
Table 14: SBI T1 Clock Rate Encoding ClkRate[1:0] "00" - Nominal "01" - Fast T1 Clocks / 2KHz 772 773
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
"1x" - Slow
771
The method for transferring DS3 link rate information across the SBI passes the encoded count of DS3 clocks between 2KHz SC1FP pulses in the same method used for T1 tributaries, but does not pass any phase information. The other difference from T1 link rate is that ClkRate[1:0] indicates whether the nominal number of clocks are generated or if four fewer or four extra clocks are generated during the SC1FP period. The format of the DS3 link rate octet is shown in Table 15. This is passed across the SBI via the Linkrate octet which follows the H3 octet in the column, see Table 19. Table 16 shows the encoding of the clock count, ClkRate[1:0], passed in the link rate octet. Table 15: DS3 Link Rate Information Link Rate Octet DS3 Format Bit # 7 0 6 0 5:4 ClkRate[1:0] 3:0 Unused
Table 16: DS3 Clock Rate Encoding ClkRate[1:0] "00" - Nominal "01" - Fast "1x" - Slow SBI Alarms The TECT3 transfers alarm conditions across the SBI bus for T1 tributaries. The TECT3 does not support alarm conditions across the SBI bus for DS3. Table 13 show the alarm indication bit, ALM, as bit 7 of the Link Rate Octet. Devices connecting to the TECT3 which do not support alarm indications must set this bit to 0 on the SBI ADD bus. The presence of an alarm condition is indicated by the ALM bit set high in the Link Rate Octet. The absence of an alarm condition is indicated by the ALM bit set low in the Link Rate Octet. In the egress direction the TECT3 can be configured to use the alarm bit to force AIS on a per link basis. DS3 Clocks / 2KHz 22368 22372 22364
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
T1 Tributary Mapping Table 17 shows the format for mapping 84 T1s within the SPE octets. The DS0s and framing bits within each T1 are easily located within this mapping for channelized T1 applications. It is acceptable for the framing bit to not carry a valid framing bit on the Add Bus since the physical layer device will provide this information. Unframed T1s use the exact same format for mapping 84 T1s into the SBI except that the T1 tributaries need not align with the frame bit and DS0 locations. The V1,V2 and V4 octets are not used to carry T1 data and are either reserved or used for control across the interface. When enabled, the V4 octet is the Link Rate octet of Tables 1 and 3. It carries alarm and clock phase information across the SBI bus. The V1 and V2 octets are unused and should be ignored by devices listening to the SBI bus. The V5 and R octets do not carry any information and are fixed to a zero value. The V3 octet carries a T1 data octet but only during rate adjustments as indicated by the V5 indicator signals, DV5 and AV5, and payload signals, SDPL and SAPL. The PPSSSSFR octets carry channel associated signaling (CAS) bits and the T1 framing overhead. The DS0 octets are the 24 DS0 channels making up the T1 link. The V1,V2,V3 and V4 octets are fixed to the locations shown. All the other octets, shown shaded for T1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2KHz multi-frame. The position of the floating T1 is identified via the V5 Indicator signals, SDV5 and SAV5, which locate the V5 octet. When the T1 tributary rate is faster than the SBI nominal T1 tributary rate, the T1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the V3 location. When the T1 tributary rate is slower than the nominal SBI tributary rate the T1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the V3 octet and delaying the octet that was originally in that position. Table 17: T1 Framing Format
COL # ROW # T1#1,1
T1#2,1-3,28 20-102 V1 -
T1#1,1
T1#2,1-3,28 104-186 -
T1#1,1
T1#2,1-3,28 188-270 -
1-18 Unused Unused Unused Unused Unused Unused Unused Unused
19 V1 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19
103 V5 DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20
187 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21
1 2 3 4 5 6 7 8
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused
DS0#22 V2 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V3 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22 V4 DS0#1 DS0#4 DS0#7 DS0#10 DS0#13 DS0#16 DS0#19 DS0#22
V2 V3 V4 -
DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23 R DS0#2 DS0#5 DS0#8 DS0#11 DS0#14 DS0#17 DS0#20 DS0#23
-
DS0#24 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24 PPSSSSFR DS0#3 DS0#6 DS0#9 DS0#12 DS0#15 DS0#18 DS0#21 DS0#24
-
The P1P0S1S2S3S4FR octet carries T1 framing in the F bit and channel associated signaling in the P1P0and S1S2S3S4bits. Channel associated signaling is optional. The R bit is reserved and is set to 0. The P1P0bits are used to indicate the phase of the channel associated signaling and the S1S2S3S4 bits are the channel associated signaling bits for the 24 DS0 channels in the T1. Table 18 shows the channel associated signaling bit mapping and how the phase bits locate the sixteen state CAS mapping as well as T1 frame alignment for super frame and extended superframe formats. When using four state CAS then the signaling bits are A1-A24, B1-B24, A1-B24, B1-B24 in place of are A1-A24, B1-
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
B24, C1-C24, D1-D24. When using 2 state CAS there are only A1-A24 signaling bits. Table 18: T1 Channel Associated Signaling bits
SF S1 S2 S3 S4 F ESF F P1 P0
A1 A5 A9 A13 A17 A21 B1 B5 B9 B13 B17 B21 C1 C5 C9 C13 C17 C21 D1 D5 D9 D13 D17 D21
A2 A6 A10 A14 A18 A22 B2 B6 B10 B14 B18 B22 C2 C6 C10 C14 C18 C22 D2 D6 D10 D14 D18 D22
A3 A7 A11 A15 A19 A23 B3 B7 B11 B15 B19 B23 C3 C7 C11 C15 C19 C23 D3 D7 D11 D15 D19 D23
A4 A8 A12 A16 A20 A24 B4 B8 B12 B16 B20 B24 C4 C8 C12 C16 C20 C24 D4 D8 D12 D16 D20 D24
F1 S1 F2 S2 F3 S3 F4 S4 F5 S5 F6 S6 F1 S1 F2 S2 F3 S3 F4 S4 F5 S5 F6 S6
M1 C1 M2 F1 M3 C2 M4 F2 M5 C3 M6 F3 M7 C4 M8 F4 M9 C5 M10 F5 M11 C6 M12 F6
00 00 00 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11
Note that in synchronous mode, the SF/ESF F-bits may have arbitrary alignment with respect to the P1P0 phase alignment bits, due to possible frame slips at the T1 level. However, CAS is always aligned to the P1P0 bits (i.e. in either synchronous or asynchronous mode). T1 tributary asynchronous timing is compensated via the V3 octet. T1 tributary link rate adjustments are optionally passed across the SBI via the V4. T1 tributary alarm conditions are optionally passed across the SBI bus via the link rate octet in the V4 location. In synchronous mode the T1 tributary mapping is fixed to that shown in Table 17 and rate justifications are not possible using the V3 octet. The clock rate
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information within the link rate octet in the V4 location is not used in synchronous mode. DS3 Tributary Mapping Table 19 shows a DS3 tributary mapped within the first synchronous payload envelope SPE1. The V5 indicator pulse identifies the V5 octet. The DS3 framing format does not follow an 8KHz frame period so the floating DS3 multi-frame located by the V5 indicator, shown in heavy border grey region in Table 19, will jump around relative to the H1 frame on every pass. In fact the V5 indicator will often be asserted twice per H1 frame, as is shown by the second V5 octet in Table 19. The V5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the H3 octet or leaving empty the octet after the H3 octet. Table 19: DS3 Framing Format
SPE COL # DS3 1 DS3 2-56
***
DS3 57
DS3 58-84
***
DS3 Col 85
SBI COL# ROW 1 2 3 4 5 6 7 8 9 1,4,7,10 Unused Unused Unused Unused Unused Unused Unused Unused 13
H1 H2 H3
16 V5 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
184 DS3 DS3 DS3 DS3 DS3 DS3 DS3 V5 DS3
268 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
Unused Linkrate Unused Unused Unused Unused Unused
Because the DS3 tributary rate is less than the rate of the grey region, padding octets are interleaved with the DS3 tributary to make up the difference in rate. Interleaved with every DS3 multi-frame are 35 stuff octets, one of which is the V5 octet. These 35 stuff octets are spread evenly across seven DS3 subframes. Each DS3 subframe is eight blocks of 85 bits. The 85 bits making up a DS3 block are padded out to be 11 octets. Table 20 shows the DS3 block 11 octet format where R indicates a stuff bit, F indicates a DS3 framing bit and I indicates DS3 information bits. Table 21 shows the DS3 multi-frame format that is packed into the grey region of Table 19. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff octet and B indicates the 11 octet DS3 block. Each row in Table 21 is a DS3 multi-frame. The DS3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after the V5 octet is added every sixth frame.
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Table 20: DS3 Block Format
Octet # Data 1 RRRFIIII 2 8*I 3 8*I 4 8*I 5 8*I 6 8*I 7 8*I 8 8*I 9 8*I 10 8*I 11 8*I
Table 21: DS3 Multi-frame Stuffing Format
V5 V5 V5 V5 V5 V5 4*R 4*R 4*R 4*R 4*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B 5*R 5*R 5*R 5*R 5*R 5*R 8*B 8*B 8*B 8*B 8*B 8*B
DS3 asynchronous timing is compensated via the H3 octet. DS3 link rate adjustments are optionally passed across the SBI via the Linkrate octet. 12.11 H-MVIP Data Format The H-MVIP data and Channel Associated Signaling interfaces on the TECT3 are able to carry all the DS0s for 28 T1s or all timeslots for 21 E1s. When Carrying timeslots from E1s the H-MVIP frame is completely filled with 128 timeslots from four E1s but when carrying DS0s from four T1s there are not enough DS0s to completely fill the 128 byte frame. Table 22 shows how the DS0s and CAS bits of four T1s are formatted in the 128 timeslot H-MVIP frame. Table 23 shows the timeslot and CAS bit H-MVIP format when in G.747 mode. The CAS bits are carried in bits 5,6,7 and 8 of each byte on the CASID[1:7] and CASED[1:7] H-MVIP buses. Table 22: Data and CAS T1 H-MVIP Format Timeslot Number 0-3 4-7 8-11 12-15 16-19 First T1 DS0 Number Undefined 1 2 3 Undefined Second T1 DS0 Number Undefined 1 2 3 Undefined Third T1 DS0 Number Undefined 1 2 3 Undefined Fourth T1 DS0 Number Undefined 1 2 3 Undefined
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20-23 24-27 28-31 32-35 * * * 108-111 112-115 116-119 120-123 124-127
4 5 6 Undefined * * * 21 Undefined 22 23 24
4 5 6 Undefined * * * 21 Undefined 22 23 24
4 5 6 Undefined * * * 21 Undefined 22 23 24
4 5 6 Undefined * * * 21 Undefined 22 23 24
Table 23: Data and CAS E1 H-MVIP Format in G.747 mode Timeslot Number 0-3 4-7 8-11 12-15 16-19 * * * 120-123 124-127 First E1 TS Number 0 1 2 3 4 * * * 30 31 Second E1 TS Number 0 1 2 3 4 * * * 30 31 Third E1 TS Number 0 1 2 3 4 * * * 30 31 Fourth E1 TS Number undefined undefined undefined undefined undefined * * * undefined undefined
The H-MVIP Common Channel Signaling interface on TECT3 carries at most 63 timeslots when in E1 mode, timeslot 16 for ISDN signaling, timeslot 15 and timeslot 31 for V5.2 interfaces. In T1 mode the CCS H-MVIP interface only carries 28 full timeslots. Table 24 shows the H-MVIP format for carrying 28 common channeling signaling channels when in T1 mode. Table 25 shows the
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H-MVIP format for carrying 63 E1 common channeling signaling channels when in G.747 mode . These formats are fixed so when a signaling or V5.2 channel is not in use the H-MVIP timeslot is undefined. Table 24: CCS T1 H-MVIP Format H-MVIP Timeslot Number 0 1 2 3 4 * * * 26 27 28 29 * * * 127 T1 Number 1 2 3 4 5 * * * 27 28 undefined undefined * * * undefined
Table 25: CCS E1 H-MVIP Format in G.747 Mode H-MVIP Timeslot Number 0 1 2 3 4 E1 Number TS 16 1 2 3 undefined 4 E1 Number TS 15 E1 Number TS 31
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5 6 7 * * * 24 25 26 27 * * * 31 32 33 34 35 * * * 58 59 * * * 63 64 65
5 6 undefined * * * 19 20 21 undefined * * * undefined 1 2 3 undefined * * * 21 undefined * * * undefined 1 2
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66 67 * * * 90 91 * * * 127 12.12 Serial Clock and Data Format
3 undefined * * * 21 undefined * * * undefined
The Serial Clock and Data interfaces are able to carry the complete payload for 28 T1s or 21 E1s. Each T1 or E1 is assigned to one transmit pin and one receive data pin for the payload. As appropriate, additional pins may exist for the T1/E1 clock, signaling bits and/or frame pulse, depending on the specific interface mode selected. The formatting of these bits is outlined in greater deail in the Functional Timing section of this document. In T1 mode, all 28 sets of clock and data pins are used in each direction. In normal E1 mode, the first 21 sets of clock and data pins are used in each direction. The clock and data pins numbered between 22 and 28 are not nd th defined, as the 22 through 28 framer blocks are not used in this mode. In ITU-T G.747 mutiplexed E1 mode, every fourth set of clock and data pins are not used in each direction. (i.e. Pins 1-3, 5-7, 9-11, 13-15, 17-19, 21-23, 25-27 are defined while pins 4, 8, 12, 16, 20, 24, and 28 are not defined.) This is because the 4th, 8th, 12th, 16th, 20th, 24th and 28th framer blocks are not used in this mode. 12.13 PRGD Pattern Generation The pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in Figure 41 below:
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Figure 41: PRGD Pattern Generator
LENGTH PS TAP
1
2
3
32
The pattern generator consists of a 32 bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length register (PL[4:0]) and the tap register (PT[4:0], when the PS bit is low). When PS is high, the pattern detector functions as a recirculating shift register, with length determined by PL[4:0]. Generating and detecting repetitive patterns When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS bit must be set to logic 1. The pattern length register must be set to (N-1), where N is the length of the desired repetitive pattern. Several examples of programming for common repetitive sequences are given below in the Common Test Patterns section. For pattern generation, the desired pattern must be written into the PRGD Pattern Insertion registers. The repetitive pattern will then be continuously generated. The generated pattern will be inserted in the output data stream, but the phase of the pattern cannot be guaranteed. For pattern detection, the PRGD will determine if a repetitive pattern of the length specified in the pattern length register exists in the input stream. It does so by loading the first N bits from the data stream, and then monitoring to see if the pattern loaded repeats itself error free for the subsequent 48 bit periods. It will repeat this process until it finds a repetitive pattern of length N, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. Note that the PRGD does NOT look for the pattern loaded into the Pattern Insertion registers, but rather automatically detects any repetitive pattern of the specified length. The precise pattern detected can be determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD Control register, and reading the Pattern Detector registers (which will then contain the 32 bits detected immediately prior to the strobe).
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Common Test Patterns The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T O.151. The register configurations required to generate these patterns and others are indicated in Table 26 and Table 27 below:
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Table 26: Pseudo Random Pattern Generation (PS bit = 0) Pattern Type 23 -1 24 -1 25-1 26 -1 27 -1 27 -1 (Fractional T1 LB Activate) 27 -1 (Fractional T1 LB Deactivate) 29 -1 (O.153) 210 -1 211 -1 (O.152, O.153) 215 -1 (O.151) 217 -1 218 -1 220 -1 (O.153) 220 -1 (O.151 QRSS bit=1) 221 -1 222 -1 223 -1 (O.151) 225 -1 228 -1 229 -1 TR 00 00 01 04 00 03 03 04 02 08 0D 02 06 02 10 01 00 11 02 02 01 LR 02 03 04 05 06 06 06 08 09 0A 0E 10 11 13 13 14 15 16 18 1B 1C IR#1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF IR#2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF IR#3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF IR#4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF TINV 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 RINV 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0
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231 -1
02
1E
FF
FF
FF
FF
0
0
Table 27: Repetitive Pattern Generation (PS bit = 1) Pattern Type All ones All zeros Alternating ones/zeros Double alternating ones/zeros 3 in 24 1 in 16 1 in 8 1 in 4 Inband loopback activate Inband loopback deactivate TR 00 00 00 00 00 00 00 00 00 00 LR 00 00 01 03 17 0F 07 03 04 02 IR#1 FF FE FE FC 22 01 01 F1 F0 FC IR#2 FF FF FF FF 00 00 FF FF FF FF IR#3 FF FF FF FF 20 FF FF FF FF FF IR#4 FF FF FF FF FF FF FF FF FF FF TINV 0 0 0 0 0 0 0 0 0 0 RINV 0 0 0 0 0 0 0 0 0 0
Notes for the Pseudo Random and Repetitive Pattern Generation Tables 1. The PS bit and the QRSS bit are contained in the PRGD Control register 2. TR = PRGD Tap Register 3. LR = PRGD Length Register 4. IR#1 = PRGD Pattern Insertion #1 Register 5. IR#2 = PRGD Pattern Insertion #2 Register 6. IR#3 = PRGD Pattern Insertion #3 Register 7. IR#4 = PRGD Pattern Insertion #4 Register 8. The TINV bit and the RINV bit are contained in the PRGD Control register
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12.14 JTAG Support The TECT3 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. Figure 42: Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
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The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital outputs. 12.14.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 43: TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
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Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
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STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out of the output, TDO, using the Shift-DR state. Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2. Figure 44: Input Observation Cell (IN_CELL)
IDCODE Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
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Figure 45: Output Cell (OUT_CELL)
Scan Chain Out EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 46: Bidirectional Cell (IO_CELL)
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 1
INPUT to internal logic
MUX
OUTPUT to pin
D C
D C
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Figure 47: Layout of Output Enable and Bidirectional Cells Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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13
FUNCTIONAL TIMING
13.1 DS3 Line Side Interface Timing All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the TECT3 registers are set to their default states). Figure 48: Receive Bipolar DS3 Stream
RCLK
LCV
RPOS
3 consec 0s
RNEG
The Receive Bipolar DS3 Stream diagram (Figure 48) shows the operation of the TECT3 while processing a B3ZS encoded DS3 stream on inputs RPOS and RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated corresponds to a valid B3ZS signature. A line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid B3ZS signature. Figure 49: Receive Unipolar DS3 Stream
RCLK RDAT RLCV
X1 BIT INFO 1 INFO 84 X2 BIT INFO 84 OR P OR M BIT C BIT INFO 1 OR F BIT INFO 2 INFO 3 INFO 4 INFO 5
LCV INDICATION
The Receive Unipolar DS3 Stream diagram (Figure 49) shows the complete DS3 receive signal on the RDAT input. Line code violation indications, detected by an upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
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Figure 50: Transmit Bipolar DS3 Stream TICLK TCLK TPOS TNEG
1 1 0 0 0 1 0
The Transmit Bipolar DS3 Stream diagram (Figure 50) illustrates the generation of a bipolar DS3 stream. The B3ZS encoded DS3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a DS3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 51: Transmit Unipolar DS3 Stream TICLK TCLK TDAT TMFP The Transmit Unipolar DS3 Stream diagram (Figure 51) illustrates the unipolar DS3 stream generation. The TMFP output marks the M-frame boundary, X1 bit, in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
X1 Nib 1 Bit 4 Nib 21 Bit 1 X2 Nib 22 Bit 4 Nib 1190 Bit 1 X1 Nib 1 Bit 4
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13.2 DS3 System Side Interface Timing Figure 52: Framer Mode DS3 Transmit Input Stream
TICLK or RCLK TDATI TFPI/TMFPI TFPO/TMFPO
INFO 82 INFO 83 INFO 84
F4
INFO 82 INFO 83 INFO 84
X1
INFO 1
INFO 2
X2
INFO 1
INFO 2
INFO 3
INFO 82 INFO 83 INFO 84
Figure 53: Framer Mode DS3 Transmit Input Stream With TGAPCLK
TGAPCLK TDATI
INFO 83 INFO 84 INFO 1 INFO 83 INFO 84 INFO 1 INFO 2 INFO 3 INFO 1 INFO 2 INFO 3 INFO 4 INFO 81 INFO 82 INFO 83
The Framer Mode DS3 Transmit Input Stream diagram (Figure 52) shows the expected format of the inputs TDATI and TFPI/TMFPI along with TICLK and the output TFPO/TMFPO when the OPMODE[1:0] bits are set to "DS3 Framer Only mode" in the Global Configuration register. If the TXMFPI bit in the DS3 Master Unchannelized Interface Options register is logic 0, then TFPI is valid, and the TECT3 will expect TFPI to pulse for every DS3 overhead bit with alignment to TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TECT3 will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the TXMFPO bit in the DS3 Master Unchannelized Interface Options register is logic 0, then TFPO is valid, and the TECT3 will pulse TFPO once every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the TECT3 will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. When the DS3 interface is loop timed by setting the LOOPT bit in the DS3 Master Data Source register, RCLK replaces TICLK as the transmit timing reference and all timing is relative to RCLK. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 53. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the active edge of TGAPCLK when TXGAPEN is set to logic 1 and on the active edge of TICLK when TXGAPEN is set to logic 0. The TDATIFALL bit in the DS3 Master Unchannelized Interface Options register selects the active edge of TICLK or TGAPCLK for sampling TDATI.
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Figure 54: Framer Mode DS3 Receive Output Stream
RSCLK RDATO INFO 82 RFPO/RMFPO ROVRHD
INFO INFO 83 84
F 4
INFO 82
INFO INFO 83 84
X 1
INFO 1
INFO 2
X 2
INFO INFO INFO 1 2 3
INFO 82
INFO INFO 84 83
Figure 55: Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK RDATO
INFO 82 INFO 83 INFO 84 INFO 82 INFO INFO 83 84 INFO 1 INFO 2 INFO INFO INFO 1 2 3 INFO 82 INFO INFO 84 83
The DS3 Framer Only Mode Receive Output Stream diagram (Figure 54) shows the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the OPMODE[1:0] bits are set to "DS3 Framer Only mode" in the Global Configuration register. Figure 54 shows the data streams when the TECT3 is configured for the DS3 receive format. If the RXMFPO bit in the DS3 Master Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse high for one RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure 54), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. Figure 55 shows the output data stream with RGAPCLK in place of RSCLK when the RXGAPEN bit in the DS3 Master Unchannelized Interface Options register set to logic 1. RGAPCLK remains high during the overhead bit positions.
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STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
13.3 SBI DROP Bus Interface Timing Figure 56: SBI DROP Bus T1 Functional Timing
SREFCLK SC1FP SDDATA[7:0] SDPL SDV5 SDDP SBIACT C1
*** *** *** *** *** *** ***
V3
V3
V3 DS0#4. V5 DS0#9.
Figure 56 illustrates the operation of the SBI DROP Bus, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting SDPL high during the V3 octet. The timing diagram also shows the location of one of the tributaries by asserting SDV5 high during the V5 octet. The SBIACT signal is shown for the case in which TECT3 is driving SPE#1 onto the SBI DROP bus. Figure 57: SBI DROP Bus DS3 Functional Timing
SREFCLK SC1FP SDDATA[7:0 ] SDPL SDV5 SDDP SBIACT C1
*** *** *** *** *** *** ***
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
Figure 57 shows three DS-3 tributaries mapped onto the SBI bus. A negative justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3 which has SDPL asserted low. The SBIACT signal is shown for the case in which TECT3 is driving SPE#2 (DS-3#2) onto the SBI DROP bus.
PROPRIETARY AND CONFIDENTIAL
187
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
13.4 SBI ADD Bus Interface Timing The SBI ADD bus functional timing for the transfer of tributaries, whether T1 or DS3, is the same as for the SBI DROP bus. The only difference is that the SBI ADD bus has one additional signal: the SAJUST_REQ output. The SAJUST_REQ signal is used to by the TECT3 in SBI master timing mode to provide transmit timing to SBI link layer devices. Figure 58: SBI ADD Bus Justification Request Functional Timing
SREFCLK SC1FP SADATA[7:0] SAPL SAV5 SADP SAJUST_REQ C1
*** *** *** *** *** *** ***
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
Figure 58 illustrates the operation of the SBI ADD Bus, using positive and negative justification requests as an example. (The responses to the justification requests would take effect during the next multi-frame.) The negative justification request occurs on the DS-3#3 tributary when SAJUST_REQ is asserted high during the H3 octet. The positive justification occurs on the DS-3#2 tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after the H3 octet. 13.5 Egress H-MVIP Link Timing The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVED[x], CASED[x] or CCSED, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 59. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbps HMVIP operation. The TECT3 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TECT3 samples the data provided on MVED[x], CASED[x] and CCSED at the 3/4 point of the data bit using the rising edge of CMV8MCLK as indicated for bit 1 (B1) of time-slot 1 (TS 1) in Figure 59. B1 is the most significant bit and B8 is the least significant bit of each octet.
PROPRIETARY AND CONFIDENTIAL
188
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 59: Egress 8.192 Mbps H-MVIP Link Timing
CMV8MCLK (16 MHz) CMVFPC (4 MHz)
CMVFPB MVED[x] CASED[x] CCSED
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
13.6 Ingress H-MVIP Link Timing The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame pulse clock, CMVFPC, data, MVID[x], CASID[x] or CCSID, and frame pulse, CMVFPB, signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 60. The falling edges of each CMVFPC are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbps HMVIP operation. The TECT3 samples CMVFPB low on the falling edge of CMVFPC and references this point as the start of the next frame. The TECT3 updates the data provided on MVID[x], CASID[x] and CCSID on every second falling edge of CMV8MCLK as indicated for bit 2 (B2) of time-slot 1 (TS 1) in Figure 60. The first bit of the next frame is updated on MVID[x], CASID[x] and CCSID on the falling CMV8MCLK clock edge for which CMVFPB is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet. Figure 60: Ingress 8.192 Mbps H-MVIP Link Timing
CMV8MCLK (16 MHz) CMVFPC (4 MHz)
CMVFPB MVID[x] CASID[x] CCSID
B8 TS 127
B1
B2
B3
B4 TS 0
B5
B6
B7
B8
B1 TS 1
PROPRIETARY AND CONFIDENTIAL
189
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
13.7 Egress Serial Clock and Data Interface Timing By convention in the following functional timing diagrams, the first bit transmitted in each channel shall be designated bit 1 and the last shall be designated bit 8. Each of the Ingress and Egress Master and Clock Modes apply to both T1 and E1 configurations with the exception of the 2.048MHz T1 Clock Slave Modes. Figure 61: T1 Egress Interface Clock Master: NxChannel Mode
Channel 24 Channel 1
ED[x] ECLK[x]
Don't Care
12 345 678
12 345 678
Figure 62: E1 Egress Interface Clock Master : NxChannel Mode
ED[x] ECLK[x]
Don't Care
123456 78
12345 678
Timeslot 23
Timeslot 25
The Egress Interface Options register is programmed to select NxChannel mode. The TPSC egress control bytes are programmed to insert the desired channels. In Figure 61, the egress control bytes for T1 channels 1 and 24 are configured to insert these channels. In Figure 62, the egress control bytes for E1 channels 23 and 25 are configured to insert these channels. ECLK[x] is gapped so that it is only active for those channels with the associated IDLE_CHAN bit cleared (logic 0). The remaining channels (with IDLE_CHAN set) contain the per-channel idle code as defined in the associated Idle Code byte. When the EDE bit in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is sampled on the falling edge of ECLK[x], and the functional timing is described by Figure 61 with the ECLK[x] signal inverted. Figure 63: T1 and E1 Egress Interface Clock Master: Clear Channel Mode
ECLK[x] ED[x]
8 12 3 4 5 6 7 81 2 3 45 6 7 8 1 2 34 56 78
PROPRIETARY AND CONFIDENTIAL
190
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
The Egress Interface is configured for the Clock Master: Clear Channel mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. ED[x] is sampled on the rising edge of the ECLK[x] output. When the the EDE bit in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is sampled on the falling edge of ECLK[x], and the functional timing is described by Figure 63 with the ECLK[x] signal inverted. Figure 64: T1 Egress Interface Clock Slave: EFP Enabled mode
CECLK CEFP ED[x] EFP[x] Channel 24 Channel 1 F-bit or Parity Channel 2 Channel 24 Channel 1 F-bit or Parity
12 34 5 6 7 8F12 3 45 6 7 8 1 2 34 56 78 12 345678F12345678
Figure 65: E1 Egress Interface Clock Slave : EFP Enabled Mode
CECLK CEFP ED[x] EFP[x] Timeslot 31 Timeslot 0 Parity bit (if enabled) Timeslot 1 Timeslot 31 Timeslot 0 Parity bit (if enabled)
1 2 3 4 5 6 7 81 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 12 3 45 67 81 2 3 45 6 78 1
The Egress Interface is configured for the Clock Slave: EFP Enabled mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. ED[x] is sampled on the active edge of CECLK and EFP[x] is updated on the falling edge of CECLK. In T1 mode, Figure 64, the CEMFP bit is written to logic 1 in the Master Egress Slave Mode Serial Interface Configuration register, so that CEFP must pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first frame bit of the multiframe. If parity checking is enabled, a parity bit should be inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high to mark the F-bit of each frame in order to indicate frame alignment to an upstream device. EFP[x] may be configured to mark superframe alignment instead by setting the EMFP bit in the T1/E1 Serial Interface Configuration register.
PROPRIETARY AND CONFIDENTIAL
191
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
In E1 mode EFP[x] may be chosen to indicate alignment of every frame or the composite CRC and Signaling multiframe alignment as shown in Figure 65, by setting the EMFP bit in the T1/E1 Serial Interface Configuration register. If parity checking is enabled, a parity bit should be inserted on ED[x] in the first bit of each frame. Figure 66: T1 Egress Interface Clock Slave: External Signaling mode
CECLK CEFP ED[x] ESIG[x]
1 2 3 4 5 6 7 8F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A BCD A BCD A BCD 12 3 45 67 8F1 2 3 45 6 78 A BC D A BCD
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
Figure 67: E1 Egress Interface Clock Slave : External Signaling Mode
CECLK CEFP ED[x] ESIG[x]
12 34 5 6 7 812 3 45 6 7 8 1 2 34 56 78 ABCD ABCD 12 3 45 67 81 2 3 45 6 78 1 A BC D
Timeslot 31 Timeslot 0 Parity bit (if enabled)
Timeslot 1
Timeslot 31 Timeslot 0 Parity bit (if enabled)
The Egress Interface is configured for the Clock slave: External Signaling Mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. ED[x] is clocked in on the active edge of CECLK. Frame alignment is specified by pulses on CEFP. ESIG[x] should carry the signaling bits for each channel in bits 5,6,7 and 8. These signaling bits will be inserted into the data stream by the T1 or E1 transmitter. If parity checking is enabled, a parity bit should be inserted on ED[x] and ESIG[x] in the first bit of each frame. The parity operates on all bits in the ED[x] and ESIG[x] streams, including the unused bits on ESIG[x].
PROPRIETARY AND CONFIDENTIAL
192
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 68: T1 Egress Interface 2.048 MHz Clock Slave: EFP Enabled Mode
CECLK CEFP ED[x] EFP[x]
F
Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Don't Care
1 2 34 5 6 7 8
F-Bit or Parity
Channel 1 Frame 1
Channel 2 Frame 1
Channel 3 Frame 1
"filler"
Channel 4 Frame 1
CECLK CEFP ED[x] EFP[x]]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch24 Ch1
The Egress Interface is configured for the Clock Slave: EFP Enabled Mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to logic 1 in the Master Egress Slave Mode Serial Interface register. In Figure 68, CEFP is configured for superframe alignment by writing CEMFP to logic 1 in the Master Egress Slave Mode Serial Interface register, so that the CEFP input must pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit of the multiframe to specify superframe alignment, instead of once every frame to specify frame alignment. If parity checking is enabled, a parity bit should be inserted on ED[x] in the first bit of each frame. The EFP[x] output will pulse high to mark the F-bit of each frame in order to indicate frame alignment to an upstream device. EFP[x] may be configured to mark superframe alignment instead by setting the EMFP bit in the T1/E1 Serial Interface Configuration register. The values of the don't-care bits are not important, except that they will be used in the backplane parity check if it is enabled.
PROPRIETARY AND CONFIDENTIAL
193
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 69: T1 Egress Interface 2.048 MHz Clock Slave: External Signaling Mode
CECLK CEFP ED[x] ESIG[x]
F
Don't Care Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ABCD ABCD ABCD
Don't Care Don't Care
1 2 34 5 6 7 8 AB CD
F-Bit or Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CECLK CEFP ED[x] ESIG[x]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch24 Ch1
The Egress Interface is configured for the 2.048 MHz Clock Slave: External Signaling Mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. The 2.048 MHz internally gapped clock mode is selected by writing CECLK2M to logic 1 in the Master Egress Slave Mode Serial Interface register. In the illustrated case, CEFP specifies frame alignment and is required to pulse high for one cycle every frame. ESIG[x] should carry the signaling bits for each channel in bits 5,6,7 and 8; the signaling bits will be inserted into the data stream by the transmitter. If parity checking is enabled, a parity bit should be inserted on ED[x] and ESIG[x] in the first bit of each frame. The values of the don't-care bits are not important, except that they will be used in the backplane parity check if it is enabled. Figure 70: T1 and E1 Egress Interface Clock Slave: Clear Channel Mode
ECLK[x] ED[x]
8 12 3 4 5 6 7 81 2 3 45 6 7 8 1 2 34 56 78
PROPRIETARY AND CONFIDENTIAL
194
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
The Egress Interface is configured for the Clock Slave: Clear Channel mode by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select register. ED[x] is clocked in on the rising edge of the ECLK[x] input. When the EDE bit in the T1/E1 Serial Interface Configuration register is set to logic 0, then ED[x] is sampled on the falling edge of ECLK[x], and the functional timing is described by Figure 70 with the ECLK[x] signal inverted. 13.8 Ingress Serial Clock and Data Interface Timing Figure 71: T1 Ingress Interface Clock Master : Full Channel Mode
ICLK[x] IFP[x] ID[x]
123456 78F1234567812345678 12345678F12345678
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
Figure 72: E1 Ingress Interface Clock Master : Full Channel Mode
ICLK[x] IFP[x] ID[x]
1 23 456 7812 345 6 7 812 34 56 7 8 12345678123456781
Timeslot 31 Timeslot 0 Parity Bit (if enabled)
Timeslot 1
Timeslot 31 Timeslot 0 Parity Bit (if enabled)
The IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register are programmed to select the Clock Master: Full Channel mode. IFP[x] is set high for one ICLK[x] period every frame. When the IMFP bit in the T1/E1 Serial Interface Configuration register are set to 1, IFP[x] pulses on the superframe frame boundaries (i.e. once every 12 or 24 frame periods when configured for T1 operation or once every CRC or signaling multiframe when configured for E1 operation). The IMFPCFG[1:0] bits select whether IFP[x] indicates E1 CRC, signaling or both CRC and signaling multiframe boundaries. If ALTIFP=1, IFP[x] pulses on every second frame or the multiframe boundary.
PROPRIETARY AND CONFIDENTIAL
195
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 73: T1 Ingress Interface Clock Master: NxChannel Mode
IFP[x] ID[x] ICLK[x] Don't Care 123456 78 12345 678
Figure 74: E1 Ingress Interface Clock Master: NxChannel Mode
IFP[x] ID[x] ICLK[x]
Don't Care
123456 78
12345 678
Timeslot 31
Timeslot 1
The IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register are programmed to select NxChannel mode. The RPSC ingress control bytes are programmed to extract the desired channels. In Figure 73, the ingress control bytes for T1 channels 2 and 24 are extracted. In Figure 74, the ingress control bytes for E1 channels 31 and 1 are extracted. ICLK[x] is gapped so that it is only active for those channels with the associated DTRKC bit set to 0. If either IMFP or ALTIFP is set, then IFP[x] will pulse only during the appropriate frames. When the IDE bit in the T1/E1 Serial Interface Configuration register bit is set, then ID[x] is updated on the rising edge of ICLK[x] and the functional timing is described by with ICLK[x] inverted. Figure 75: T1 and E1 Ingress Interface Clock Master: Clear Channel Mode
I CLK[x] I D[x]
8 12 3 4 5 6 7 81 2 3 45 6 7 8 1 2 34 56 78
The Ingress Interface is configured for the Clock Slave: Clear Channel mode by writing to IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register. ID[x] is updated on the falling edge of the ICLK[x] input. When the IDE bit in the T1/E1 Serial Interface Configuration register is set to logic 1, then ID[x] is updated on the rising edge of ICLK[x], and the functional timing is described by Figure 75 with the ICLK[x] signal inverted.
PROPRIETARY AND CONFIDENTIAL
196
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 76: T1 Ingress Interface Clock Slave: External Signaling Mode
CICLK CIFP ID[x] ISIG[x]
1 2 3 4 5 6 7 8F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A BCD A BCD A BCD 12 3 45 67 8F1 2 3 45 6 78 A BC D A BCD
Channel 24 Channel 1 F-bit or Parity
Channel 2
Channel 24 Channel 1 F-bit or Parity
Figure 77: E1 Ingress Interface Clock Slave: External Signaling Mode
CICLK CIFP ID[x] ISIG[x]
1234 5678123456781 23456 78 ABCD ABCD 12 3 45 67 8 1 2 3 45 6 781 A BCD
Timeslot 31
Timeslot 0
Timeslot 1
Timeslot 31
Timeslot 0
The Ingress Interface is programmed for Clock Slave mode by setting the IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP. CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to carry a parity bit during the first bit of each frame. In External Signaling Mode, ISIG[x] is active and is aligned as shown.
PROPRIETARY AND CONFIDENTIAL
197
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 78: T1 Ingress Interface 2.048 MHz Clock Slave: External Signaling Mode
CICLK CIFP ID[x] ISIG[x]
F
Don't Care Don't Care
1 2 3 4 5 67 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ABCD ABCD ABCD
Don't Care Don't Care
1 2 34 5 6 7 8 AB C D
F-Bit or Parity
Channel 1
Channel 2
Channel 3
"filler"
Channel 4
CICLK CIFP ID[x] ISIG[x]
Ch24 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch23 Ch 24 Ch1
The Ingress Interface is programmed for Clock Slave mode by setting the IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register. The 2.048 MHz internally-gapped clock mode is selected by setting the CICLK2M bit to logic 1 in the Master Ingress Slave Mode Serial Interface Configuration register. ID[x] is timed to the active edge of CICLK, and is frame-aligned to CIFP. CIFP need not be provided every frame. ID[x] and ISIG[x] may be configured to carry a parity bit during the first bit of each frame. The values of the filler bits will depend on the exact configuration of the TECT3, and they will be included in the parity calculation.
PROPRIETARY AND CONFIDENTIAL
198
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
14
ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 28: Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Supply Voltage Supply Voltage Supply Voltage Voltage on Any Pin (note 3) Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature Notes on Power Supplies: 1. VDD3.3 and VDDQ should power up before VDD2.5. 2. VDD3.3 and VDDQ should not be allowed to drop below the VDD2.5 voltage level except when VDD2.5 is not powered. 3. All pins on the TECT3 are 5V tolerant. TJ IIN TST VDD2.5 VDD3.3 VDDQ VIN Symbol Value -40 to +85 -40 to +125 -0.3 to + 3.5 -0.3 to + 4.6 -0.3 to + 4.6 -0.3 to + 5.5 1000 100 20 +230 +150 Units C C VDC VDC VDC VDC V mA mA C C
PROPRIETARY AND CONFIDENTIAL
199
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
15
D.C. CHARACTERISTICS TA = -40C to +85C, VDD3.3 = 3.3V 10%, VDD2.5 = 2.5V 8% (Typical Conditions: TA = 25C, VDD3.3 = 3.3V, VDDQ = 3.3V, VDD2.5 = 2.5V) Table 29: D.C. Characteristics
Symbol Parameter Min Typ Max Units Conditions
VDD3.3 VDDQ VDD2.5 VIL VIH VOL
Power Supply Power Supply Power Supply Input Low Voltage Input High Voltage Output or Bidirectional Low Voltage
2.97 2.97 2.3 -0.5 2.0
3.3 3.3 2.5
3.63 3.63 2.7 0.6 5.5 0.4
Volts Volts Volts Volts Volts Volts Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -4mA for D[7:0], LAOE, RECVCLK1, RECVCLK2, MVID[7:0], CASID[7:0], CCSID, TCLK, TPOS/TDAT, TNEG/TMFP, RGAPCLK/RSCLK, RDATAO, RFPO/RMFPO, ROVRHD, TFPO/TMFPO/TGAPCLK, SBIACT, IOL = -8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SC1FP, IOL = -2mA for others. Note 3
VOH
Output or Bidirectional High Voltage
2.4
Volts
VDD = min, IOH = 4mA for D[7:0], LAOE, RECVCLK1, RECVCLK2, MVID[7:0], CASID[7:0], CCSID, TCLK, TPOS/TDAT, TNEG/TMFP, RGAPCLK/RSCLK, RDATAO, RFPO/RMFPO, ROVRHD, TFPO/TMFPO/TGAPCLK, SBIACT, IOH = 8mA for SDDATA[7:0], SDDP, SDPL, SDV5, SAJUST_REQ, SC1FP, IOH = 2mA for others. Note 3
PROPRIETARY AND CONFIDENTIAL
200
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VT+
Reset Input High Voltage
2.0
5.5
Volts
TTL Schmidt
VT-
Reset Input Low Voltage
-0.2
0.6
Volts
VTH
Reset Input Hysteresis Voltage
1.2
0.5
Volts
IILPU IIHPU IIL IIH CIN
Input Low Current Input High Current Input Low Current Input High Current Input Capacitance
+10 -10 -10 -10 5
+100 +10 +10 +10
A A A A pF
VIL = GND. Notes 1, 3,4 VIH = VDD. Notes 1, 3 VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF
COUT
Output Capacitance
5
pF
Excluding Package, Package Typically 2 pF
CIO
Bidirectional Capacitance
5
pF
Excluding Package, Package Typically 2 pF
IDDOP1
Operating Current 30
270
mA mA
VDD2.5 = 2.7V VDD3.3 = 3.63 V Outputs Unloaded, DS3 to M13 multiplexing, SBI backplane with H-MVIP CAS mode.
Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Typical values are given as a design aid. The product is not tested to the typical values given in the data sheet.
PROPRIETARY AND CONFIDENTIAL
201
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.3V 10%, VDD2.5 = 2.5V 8%) Table 30: Microprocessor Interface Read Access Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state Min 10 5 10 10 20 0 5 40 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL
202
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 79: Microprocessor Interface Read Timing tSAR A[13:0] tS ALR tVL ALE tSLR (CSB+RDB) tZ INTH INTB tHLR tHALR
Valid
Address
tH AR
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable.
PROPRIETARY AND CONFIDENTIAL
203
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
5. Parameter tHAR is not applicable if address latching is used. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Table 31: Microprocessor Interface Write Access Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW TVWR Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 20 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 80: Microprocessor Interface Write Timing
A[9:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
17
TECT3 TIMING CHARACTERISTICS (TA = -40C to +85C VDD3.3 = 3.3V 10%, VDD2.5 = 2.5V 8%) Table 32: RTSB Timing Symbol tVRSTB Description RSTB Pulse Width Min 100 Max Units ns
Figure 81: RSTB Timing
tV RSTB RSTB
Table 33: DS3 Transmit Interface Timing Symbol fTICLK t0TICLK t1TICLK tSTFPI Description TICLK Frequency TICLK minimum pulse width low TICLK minimum pulse width high TFPI/TMFPI to TICLK Set-up Time (LOOPT=0) TFPI/TMFPI to RCLK Set-up Time (LOOPT=1) (See Note 1) TFPI/TMFPI to TICLK Hold Time (LOOPT=0) TFPI/TMFPI to RCLK Hold Time (LOOPT=1) (See Note 2) TDATI to TICLK Set-up Time (LOOPT = 0) TDATI to RCLK Set-up Time (LOOPT = 1) (See Note 1) TDATI to TICLK Hold Time (LOOPT = 0) TDATI to RCLK Hold Time (LOOPT = 1) (S N t 2)
206
Min
Max Units 52 MHz ns ns ns
7.7 7.7 5 5 1 1 5 5 1 1
tHTFPI
ns
TSTDATI
ns
THTDATI
ns
PROPRIETARY AND CONFIDENTIAL
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
(See Note 2) TPTFPO TSTGAP THTGAP TPTCLK TPTPOS TPTNEG tPTPOS2 TPTNEG2 TICLK High to TPFO Prop Delay (See Note 3 and 4) TDATI to TGAPCLK Set-up Time (See Notes 1 and 5) TDATI to TGAPCLK Hold Time (See Note 2 and 5) TICLK Edge to TCLK Edge Prop Delay (See Notes 3 and 4) TCLK Edge to TPOS/TDAT Prop Delay (See Notes 3 and 4) TCLK Edge to TNEG/TMFP Prop Delay (See Notes 3 and 4) TICLK High to TPOS/TDAT Prop Delay (See Notes 3 and 4) TICLK High to TNEG/TMFP Prop Delay (See Notes 3 and 4) 2 3 2 2 -1 -1 2 2 13 5 5 13 13 16 ns ns ns ns ns ns ns ns
Notes on DS3 Transmit Interface Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 4. Maximum and minimum output propagation delays are measured with a 20 pF load on all the outputs. 5. Setup and hold times relative to TGAPCLK are measured with a 20 pF load on aTGAPCLK.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 82: DS3 Transmit Interface Timing TICLK/RCLK tS TFPI TFPI/TMFPI tH TFPI
TICLK/RCLK tS TDATI TDATI tH TDATI
TICLK/RCLK tPTFPO TFPO/TMFPO
TGAPCLK tS TGAP TDATI tH TGAP
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
TICLK=0, TRISE=0
TICLK=0, TRISE=1
TICLK=1, TRISE=X
TICLK
TICLK
TICLK
tPTCLK tPTCLK
TCLK TCLK TCLK
tP TPOS
TPOS/TDAT TPOS/TDAT
tP TPOS
TPOS/TDAT
tPTPOS2
tP TNEG
TNEG/TMFP TNEG/TMFP
tP TNEG
TNEG/TMFP
tPTNEG2
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 34: DS3 Receive Interface Timing Symbol fRCLK t0RCLK t1RCLK tSRPOS tHRPOS tSRNEG tHRNEG tPRDATO tPRFPO tPROVRHD tPRGAP Description RCLK Frequency RCLK minimum pulse width low RCLK minimum pulse width high RPOS/RDAT Set-up Time (See Note 1) RPOS/RDAT Hold Time (See Note 2) RNEG/RLCV Set-Up Time (See Note 1) RNEG/RLCV Hold Time (See Note 2) RSCLK Edge to RDATO Prop Delay (See Notes 3 and 4) RSCLK Edge to RFPO/RMFPO Prop Delay (See Notes 3 and 4) RSCLK Edge to ROVRHD Prop Delay (See Notes 3 and 4) RGAPCLK Edge to RDATO[x] Prop Delay (See Notes 3 and 4) 7.7 7.7 4 1 4 1 2 2 2 3 12 12 12 11 Min Max Units 52 MHz ns ns ns ns ns ns ns ns ns ns
Notes on DS3 Transmit Interface Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 4. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 83: DS3 Receive Interface Timing RCLK tS RPOS RPOS/RDAT tS RNEG RNEG/RLCV tH RNEG tH RPOS
RSCLK tP RDATO RDATO tP RFPO RFPO/RMFPO tPROVRHD ROVRHD Dashed line RSCLK represents behaviour when RSCLKR register bit = 1.
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RGAPCLK tP RGAP RDATO Dashed line RSCLK represents behaviour when RSCLKR register bit = 1.
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Table 35: SBI ADD BUS Timing (Figure 84) Symbol Description SREFCLK Frequency SREFCLK Duty Cycle tSSBIADD tHSBIADD tPSBIADD tZSBIADD All SBI ADD BUS Inputs Set-Up Time to SREFCLK (See Note 1) All SBI ADD BUS Inputs Hold Time to SREFCLK (See Note 2) SREFCLK to SAJUST_REQ Valid (See Notes 3 and 4) SREFCLK to SAJUST_REQ Tristate (See Note 5) Min 19.44 -50 ppm 40 4 0.75 2 2 20 20 Max 19.44 +50 ppm 60 Units MHz % ns ns ns ns
Notes on SBI Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 4. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs. 5. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 84: SBI ADD BUS Timing
SREFCLK tSSBIADD tHSBIADD
SC1FP SADATA[7:0] SADP,SAPL SAV5
tPSBIADD tZSBIADD SAJUST_REQ
Table 36: SBI DROP BUS Timing (Figure 85 to Figure 86) Symbol tPSBIDROP tPSBIACT tZSBIDROP TPOUTEN tZOUTEN tSDET tHDET Description SREFCLK to SBI DROP BUS Outputs Valid (See Notes 1 and 2) SREFCLK to SBIACT Output Valid (See Notes 1 and 3) SREFCLK to All SBI DROP BUS Outputs Tristate (See Note 4) SBIDET[1] and SBIDET[0] low to All SBI DROP BUS Outputs Valid (See Notes 1 and 2) SBIDET[1] and SBIDET[0] high to All SBI DROP BUS Outputs Tristate (See Note 4) SBIDET[n] Set-Up Time to SREFCLK (See Notes 5) SBIDET[n] Hold Time to SREFCLK (See Notes 6) Min 2 2 2 2 Max 20 19 12 15 Units ns ns ns ns
2 4 0
12
ns ns ns
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Notes on SBI Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 100 pF load on all the outputs. 3. Maximum and minimum output propagation delay is measured with a 50pF load. 4. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 85: SBI DROP BUS Timing
SREFCLK tPSBIDROP SDDATA[7:0] SDDP, SDPL SDV5 tPSBIACT SBIACT tZSBIDROP SDDATA[7:0] SDDP, SDPL SDV5 Figure 86: SBI DROP BUS Collision Avoidance Timing
SREFCLK tSDET SBIDET[n] tPOUTEN SDDATA[7:0] SDDP, SDPL SDV5 tZOUTEN tHDET
PROPRIETARY AND CONFIDENTIAL
216
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PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 37: H-MVIP Egress Timing (Figure 87) Symbol Description CMV8MCLK Frequency (See Note 3) CMV8MCLK Duty Cycle CMVFPC Frequency (See Note 4) CMVFPC Duty Cycle tPMVC TSHMVED tHHMVED TSMVFPB THMVFPB CMV8MCLK to CMVFPC skew MVED[7:1], CASED[7:1], CCSED SetUp Time MVED[7:1], CASED[7:1], CCSED Hold Time CMVFPB Set-Up Time (See Note 1) CMVFPB Hold Time (See Note 2) Min 16.368 40 4.092 40 -10 5 5 5 5 Max 16.400 60 4.100 60 10 Units MHz % MHz % ns ns ns ns ns
Notes on H-MVIP Egress Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Measured between any two CMV8MCLK falling edges. 4. Measured between any two CMVFPC falling edges.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 87: H-MVIP Egress Data & Frame Pulse Timing
CMVFPC tSMVFPB CMVFPB tPMVC CMV8MCLK tSHMVED tHHMVED tHMVFPB
MVED[x] CASED[x] CCSED
Table 38: H-MVIP Ingress Timing (Figure 88) Symbol tPHMVID Description CMV8MCLK Low to MVID[7:1], CASID[7:1], CCSID Valid (See Notes 1 and 2) Min 5 Max 25 Units ns
Notes on H-MVIP Ingress Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 88: H-MVIP Ingress Data Timing
CMV8MCLK tPHMVID MVID[x] CASID[x] CCSID
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 39: XCLK Input (Figure 89) Symbol tLXCLK tHXCLK tXCLK Description XCLK Low Pulse Width4 XCLK High Pulse Width4 XCLK Period (typically 1/37.056 MHz 32 ppm for T1 operation or 1/49.152 MHz for E1 operation)5 Min 8 8 20 Max Units ns ns ns
Figure 89: XCLK Input Timing
tH
XCLK
XCLK
t L XCLK
t
XCLK
PROPRIETARY AND CONFIDENTIAL
220
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 40: Egress Interface Timing - Clock Slave: EFP Enabled Mode (Figure 90) Symbol Description Common Egress Clock Frequency1,2(Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm for T1 modes and 2.048 MHz 50ppm for E1 modes) t1CECLK t0CECLK t1CECLK t0CECLK tSCECLK tHCECLK tPEFP1 Common Egress High Pulse Width2,4 (XCLK = 37.056 MHz) Common Egress Low Pulse Width2,4 (XCLK = 37.056 MHz) Common Egress High Pulse Width2,4 (XCLK = 49.152 MHz) Common Egress Low Pulse Width2,4 (XCLK = 49.152 MHz) CECLK to Input Set-up Time7,9 CECLK to Input Hold Time8,9 CECLK to EFP[x] Propagation delay9,10,11 20 20 5 100 ns ns ns 145 ns 145 ns 167 ns Min 1.5 Max 2.1 Units MHz
167
ns
Figure 90: Egress Interface Timing - Clock Slave: EFP Enabled Mode
CEFP ED[x] Valid tS CECLK tHCECLK CECLK t0 CECLK t1 CECLK
EFP[x] tP EFP1
Valid
PROPRIETARY AND CONFIDENTIAL
221
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 41: Egress Interface Timing - Clock Slave: External Signaling (Figure 91) Symbol Description Common Egress Clock Frequency1,2(Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm for T1 modes and 2.048 MHz 50ppm for E1 modes) t1CECLK t0CECLK t1CECLK t0CECLK tSCECLK tHCECLK Common Egress High Pulse Width2,4 (XCLK = 37.056 MHz) Common Egress Low Pulse Width2,4 (XCLK = 37.056 MHz) Common Egress High Pulse Width2,4 (XCLK = 49.152 MHz) Common Egress Low Pulse Width2,4 (XCLK = 49.152 MHz) CECLK to Input Set-up Time7,9 CECLK to Input Hold Time8,9 20 20 ns ns 145 ns 145 ns 167 ns Min 1.5 Max 2.1 Units MHz
167
ns
Figure 91: Egress Interface Timing - Clock Slave: External Signaling Mode
CEFP ED[x] ESIG[x]
Valid
tS CECLK tHCECLK t0 CECLK
CECLK
t1 CECLK
PROPRIETARY AND CONFIDENTIAL
222
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 42: Egress Interface Input Timing - Clock Master : NxChannel Mode (Figure 92) Symbol tSECLK tHECLK Description ECLK[x] to ED[x] Set-up Time7,9 ECLK[x] to ED[x] Hold Time8,9 Min 30 30 Max Units ns ns
Figure 92: Egress Interface Input Timing - Clock Master : NxChannel Mode
ED[x] Valid tS ECLK tHECLK ECLK[x]
PROPRIETARY AND CONFIDENTIAL
223
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 43: Egress Interface Input Timing - Clock Master : Clear Channel Mode (Figure 92) Symbol tSECLK tHECLK Description ECLK[x] to ED[x] Set-up Time7,9 ECLK[x] to ED[x] Hold Time8,9 Min 30 30 Max Units ns ns
Figure 93: Egress Interface Input Timing - Clock Master : Clear Channel Mode
ED[x] Valid tS ECLK tHECLK ECLK[x]
Note: ECLK[x] is an output derived from CECLK or CTCLK.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 44: Egress Interface Input Timing - Clock Master : Serial Data and HMVIP CCS Mode (Figure 92) Symbol tSICLK tHICLK Description ICLK[x] to ED[x] Set-up Time7,9 ICLK[x] to ED[x] Hold Time8,9 Min 30 30 Max Units ns ns
Figure 94: Egress Interface Input Timing - Clock Master : Serial Data and HMVIP CCS Mode ED[x] Valid tS ICLK tHICLK ICLK[x]
Note: ICLK[x] is an output derived from CMV8MCLK.
PROPRIETARY AND CONFIDENTIAL
225
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 45: Egress Interface Input Timing - Clock Slave : Clear Channel Mode (Figure 92) Symbol tSECLK tHECLK Description ECLK[x] to ED[x] Set-up Time7,9 ECLK[x] to ED[x] Hold Time8,9 Min 30 30 Max Units ns ns
Figure 95: Egress Interface Input Timing - Clock Slave : Clear Channel Mode ED[x] Valid tS ECLK tHECLK ECLK[x] Note: ECLK[x] is an input.
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 46: Ingress Interface Timing - Clock Slave Modes (Figure 96) Symbol Description Common Ingress Clock Frequency1,2 (Typically 1.544 MHz 130 ppm or 2.048 MHz 130 ppm for T1 modes and 2.048 MHz 50ppm for E1 modes) t1CICLK t0CICLK t1CICLK t0CICLK tSCICLK tHCICLK tPCICLK Common Ingress High Pulse Width2,4 (XCLK = 37.056 MHz) Common Ingress Low Pulse Width2,4 (XCLK = 37.056 MHz) Common Ingress High Pulse Width2,4 (XCLK = 49.152 MHz) Common Ingress Low Pulse Width2,4 (XCLK = 49.152 MHz) CICLK to CIFP Set-up Time7,9 CICLK to CIFP Hold Time8,9 CICLK to Ingress Output Prop. Delay9,10,11 20 20 5 100 ns ns ns 145 ns 145 ns 167 ns Min 1.5 Max 2.1 Units MHz
167
ns
PROPRIETARY AND CONFIDENTIAL
227
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 96: Ingress Interface Timing - Clock Slave Modes CIFP Valid tS CICLK tHCICLK CICLK ID[x] ISIG[x] IFP[x] tP CICLK t0 CICLK t1 CICLK
Valid
PROPRIETARY AND CONFIDENTIAL
228
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 47: Ingress Interface Timing - Clock Master Modes (Figure 97) Symbol tPICLK Description ICLK[x] to Ingress Output Prop. Delay9,10,11 Min -20 Max 20 Units ns
Figure 97: Ingress Interface Timing - Clock Master Modes
ICLK[x]
ID[x] IFP[x] tP ICLK
Valid
PROPRIETARY AND CONFIDENTIAL
229
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 48: Transmit Line Interface Timing (Figure 98) Symbol Description Min Max 2.1 Units MHz
CTCLK Frequency (when used for TJAT 1.5 REF), typically 1.544 MHz 130 ppm for T1 operation or 2.048 MHz 50 ppm for E1 operation2,3,6 tHCTCLK tLCTCLK CTCLK High Duration4 (when used for TJAT REF) CTCLK Low Duration4 (when used for TJAT REF) 100 100
ns ns
Figure 98: Transmit Line Interface Timing
t HCTCLK
CTCLK
t L CTCLK
t CTCLK
Notes on Ingress and Egress Serial Interface Timing:
1. CECLK and CICLK can be gapped and/or jittered clock signals subject to the minimum high and low times shown. These specifications correspond to nominal XCLK input frequencies. 2. Guaranteed by design for nominal XCLK input frequency (37.056 MHz 100 ppm for T1 modes and 49.152 MHz 50ppm for E1 modes). 3. CTCLK can be a jittered clock signal subject to the minimum high and low times shown. These specifications correspond to nominal XCLK input frequency of 37.056 MHz 100 ppm for T1 modes and 49.152 MHz 50ppm for E1 modes. 4. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps.
PROPRIETARY AND CONFIDENTIAL
230
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
5. XCLK frequency must be 24x the line rate 32 ppm when TJAT is freerunning or referenced to a derivative of XCLK. XCLK may be 100 ppm if an accurate reference is provided to TJAT. 6. CTCLK can be a jittered clock signal subject to the minimum high and low durations tHCTCLK, tLCTCLK. These durations correspond to nominal XCLK input frequency. 7. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 8. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 9. Setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 10. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 11. Output propagation delays are measured with a 50 pF load on all outputs with the exception of the high speed DS3 outputs (TCLK, TPOS/TDAT, TNEG/TMFP). The TCLK, TPOS/TDAT, TNEG/TMFP output propagation delays are measured with a 20 pF load.
PROPRIETARY AND CONFIDENTIAL
231
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Table 49: JTAG Port Interface Symbol Description Min Max Units
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 100 50 100 2 100
1 60
MHz % ns ns ns ns
100
ns ns
PROPRIETARY AND CONFIDENTIAL
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HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
Figure 99: JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
PROPRIETARY AND CONFIDENTIAL
233
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18
ORDERING AND THERMAL INFORMATION Table 50: Ordering and Thermal Information Part No. Description
PM4328-PI
324 Plastic Ball Grid Array (PBGA)
Table 51: Thermal information - Theta Ja vs. Airflow
Theta JA (C/W) @ specified power Dense Board
Convection
35.3
Forced Air (Linear Feet per Minute) 100 200 300 400 500
31.0 27.9 25.9 24.5 23.6
JEDEC Board
20.5
18.8
17.7
16.8
16.3
15.8
PROPRIETARY AND CONFIDENTIAL
234
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
19
MECHANICAL INFORMATION Figure 100: 324 Pin PBGA 23x23mm Body
0 .2 0 (4X )
D D1
A1 BAL L PAD CORNER
A
0.30 M C A B 0.10 M C B
22 21 20 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3 2 1 19 11
A1 BAL L CORNER
e
A1 BAL L INDICATOR
E1
E
45 o C HAM F ER 4 PLA CES
J I
A B C D E F G H J K L M N P R T U V W Y AA AB
b "d" DIA. 3 PLA CES
TO P VIEW
C A
30 o TYP
BO TT OM VIEW
bbb C
aaa C
C
A1
A2
SEATING PLA NE
SID E VIEW
NO TES: 1) ALL DIM EN SIO NS IN M ILLIM ET ER . 2) DIME NSIO N aaa DENO TE S C OP LANA RIT Y. 3) DIME NSIO N bbb DE NO TES PAR ALLEL.
1.82 2.03 2.22
2.07 2.28 2.49
0.40 0.50 0.60
1.12 1.17 1.22 23.00
19.00 19.50 20.20
0.30 0.36 0.40
0.55 0.61 0.67 23.00
19.00 19.50 20.20 1.00 1.00
0.50 0.63 0.70 1.00 1.00 0.15 0.35
PROPRIETARY AND CONFIDENTIAL
235
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
NOTES
PROPRIETARY AND CONFIDENTIAL
236
STANDARD PRODUCT DATASHEET PMC-2011596 ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER AND M13 MULTIPLEXER
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2011596(R1) ref PMC-2011465 (R1) Issue date: August 2001
PMC-Sierra, Inc..
8555 Baxter Place Burnaby, BC Canada V5A 4V7 _604 .415.6000

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